Document
CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT
Integrated Device Technology, Inc.
IDT72401 IDT72402 IDT72403 IDT72404
FEATURES:
• • • • • • • • • • • • • • • • • • First-ln/First-Out Dual-Port memory 64 x 4 organization (IDT72401/03) 64 x 5 organization (IDT72402/04) IDT72401/02 pin and functionally compatible with MMI67401/02 RAM-based FIFO with low falI-through time Low-power consumption — Active: 175mW (typ.) Maximum shift rate — 45MHz High data output drive capability Asynchronous and simultaneous read and write Fully expandable by bit width Fully expandable by word depth IDT72403/04 have Output Enable pin to enable output data High-speed data communications applications High-performance CMOS technology Available in CERDIP, plastic DIP and SOIC Military product compliant to MlL-STD-883, Class B Standard Military Drawing #5962-86846 and 5962-89523 is listed on this function. Industrial temperature range (–40°C to +85°C) is available, tested to military electrical specifications
DESCRIPTION:
The IDT72401 and IDT72403 are asynchronous highperformance First-ln/First-Out memories organized 64 words by 4 bits. The IDT72402 and IDT72404 are asynchronous high-performance First-ln/First-Out memories organized as 64 words by 5 bits. The IDT72403 and IDT72404 also have an
Output Enable (OE) pin. The FlFOs accept 4-bit or 5-bit data at the data input (D0-D3, 4). The stored data stack up on a firstin/first-out basis. A Shift Out (SO) signal causes the data at the next to last word to be shifted to the output while all other data shifts down one location in the stack. The Input Ready (IR) signal acts like a flag to indicate when the input is ready for new data (IR = HIGH) or to signal when the FIFO is full (IR = LOW). The Input Ready signal can also be used to cascade multiple devices together. The Output Ready (OR) signal is a flag to indicate that the output remains valid data (OR = HIGH) or to indicate that the FIFO is empty (OR = LOW). The Output Ready can also be used to cascade multiple devices together. Width expansion is accomplished by logically ANDing the Input Ready (IR) and Output Ready (OR) signals to form composite signals. Depth expansion is accomplished by tying the data inputs of one device to the data outputs of the previous device. The Input Ready pin of the receiving device is connected to the Shift Out pin of the sending device and the Output Ready pin of the sending device is connected to the Shift In pin of the receiving device. Reading and writing operations are completely asynchronous allowing the FIFO to be used as a buffer between two digital machines of widely varying operating frequencies. The 45MHz speed makes these FlFOs ideal for high-speed communication and controller applications. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
SI IR D 0-3 D4 (IDT72402 and IDT72404) MR DATA IN INPUT CONTROL LOGIC WRITE POINTER WRITE MULTIPLEXER Q 0-3 Q 4 (IDT72402 and IDT72404) OUTPUT CONTROL LOGIC SO OR
2747 drw 01
OUTPUT ENABLE
OE (IDT72403 and IDT72404)
MEMORY ARRAY
DATA OUT
MASTER RESET
READ MULTIPLEXER READ POINTER
The IDT logo is a registered trademark of Integrated Device Technology, Inc. FAST is a trademark of National Semiconductor, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
SEPTEMBER 1996
DSC-2747/7
5.01
1
IDT72401, IDT72402, IDT72403, IDT72404 CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
IDT72401/IDT72403 IDT72402/IDT72404 (IDT72404 Only)
NC/OE(1) IR SI D0 D1 D2 D3 GND
1 2 3 4 5 6 7 8
16 15
P16-1, D16-1 & S016-1
14 13 12 11 10 9
Vcc SO OR Q0 Q1 Q2 Q3 MR
2747 drw 02
DIP/SOIC TOP VIEW
NC/OE(2) IR SI D0 D1 D2 D3 D4 GND
1 2 3 4 5 6 7 8 9
18 17 16
P18-1, D18-1 & S018-1
15 14 13 12 11 10
Vcc SO OR Q0 Q1 Q2 Q3 Q4 MR
2747 drw 03
DIP/SOIC TOP VIEW
OE NC IR SI D0 D1 D2 D3 D4 GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
Vcc NC SO OR Q0 Q1 Q2 Q3 Q4 MR
2747 drw 04
NOTES: 1. Pin 1: NC - No Connection IDT72401, OE - IDT72403 2. Pin 1: NC - No Connection IDT72402,OE - IDT72404
CERPACK TOP VIEW
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM Rating Terminal Voltage with Respect to GND Operating Temp. Temperature Under Bias Storage Temp. DC Output Current Commercial –0.5 to +7.0 Military –0.5 to +7.0 Unit V
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VCC GND VIH VIL(1) Parameter Mil. Supply Voltage Com'l. Supply Voltage Supply Voltage Input High Voltage Input High Voltage Min. 4.5 4.5 0 2.0 — Typ. 5.0 5.0 0 — — Max. Unit 5.5 5.5 0 — 0.8 V V V V V
2747 tbl 02
TA TBIAS TSTG IOUT
0 to +70 –55 to +125 –55 to +125 50
–55 to +125 –65 to +135 –65 to +150 50
°C °C °C mA
NOTE: 1. 1.5V undershoots are allowed for 10ns once per cycle.
NOTE: 2747 tbl 01 1. Stresses greater than those listed und.