61S6432

IS61S6432 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Pentium™ or linear burst sequence control using MODE input Three chip enables for simple depth expansion and address pipelining Common data inputs and data outputs Power-down control by ZZ input JEDEC 100-Pin TQFP and PQFP package Single +3.3V power supply Two Clock enables and one Clock disable to eliminate multiple bank bus contention Control pins mode upon power-up: – MODE in interleave burst mode – ZZ in normal operation mode These control pins can be connected to GNDQ or VCCQ to alter their power-up state Industrial temperature available ISSI DESCRIPTION ® JUNE 2001 The ISSI IS61S6432 is a high-speed, low-power synchronous static RAM designed to provide a burstable, high-performance, secondary cache for the Pentium™, 680X0™, and PowerPC™ microprocessors. It is organized as 65,536 words by 32 bits, fabricated with ISSI's advanced CMOS technology. The device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edgetriggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write cont...