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74AC251 Dataheets PDF



Part Number 74AC251
Manufacturers Fairchild Semiconductor
Logo Fairchild Semiconductor
Description 8-Input Multiplexer
Datasheet 74AC251 Datasheet74AC251 Datasheet (PDF)

74AC251 • 74ACT251 8-Input Multiplexer with 3-STATE Output November 1988 Revised November 1999 74AC251 • 74ACT251 8-Input Multiplexer with 3-STATE Output General Description The AC/ACT251 is a high-speed 8-input digital multiplexer. It provides, in one package, the ability to select one bit of data from up to eight sources. It can be used as universal function generator to generate any logic function of four variables. Both true and complementary outputs are provided. Features s ICC reduced b.

  74AC251   74AC251



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74AC251 • 74ACT251 8-Input Multiplexer with 3-STATE Output November 1988 Revised November 1999 74AC251 • 74ACT251 8-Input Multiplexer with 3-STATE Output General Description The AC/ACT251 is a high-speed 8-input digital multiplexer. It provides, in one package, the ability to select one bit of data from up to eight sources. It can be used as universal function generator to generate any logic function of four variables. Both true and complementary outputs are provided. Features s ICC reduced by 50% s Multifunctional capability s On-chip select logic decoding s Inverting and noninverting 3-STATE outputs s Outputs source/sink 24 mA s ACT251 has TTL-compatible inputs Ordering Code: Order Number 74AC251SC 74AC251SJ 74AC251MTC 74AC251PC 74ACT251SC 74ACT251MTC 74ACT251PC Package Number M16A M16D MTC16 N16E M16A MTC16 N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide www.DataSheet4U.com 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names S0–S2 OE I0–I7 Z Z Select Inputs 3-STATE Output Enable Input Multiplexer Inputs 3-STATE Multiplexer Output Complementary 3-STATE Multiplexer Output Description FACT is a trademark of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation DS009945 www.fairchildsemi.com 74AC251 • 74ACT251 Functional Description This device is a logical implementation of a single-pole, 8position switch with the switch position controlled by the state of three Select inputs, S0, S1, S2. Both true and complementary outputs are provided. The Output Enable input (OE) is active LOW. When it is activated, the logic function provided at the output is: Z = OE • (I0 • S0 • S1 • S2 + I1• S0 • S1 • S2 + I2 • S0 • S1 • S2 + I3 • S0 • S1 • S2 + I4 • S0 • S1 • S2 + I5 • S0 • S1 • S2 + I6 • S0 • S1 • S2 + I7 • S0 • S1 • S2) When the Output Enable is HIGH, both outputs are in the high impedance (High Z) state. This feature allows multiplexer expansion by tying the outputs of up to 128 devices together. When the outputs of the 3-STATE devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. The Output Enable signals should be designed to ensure there is no overlap in the active-LOW portion of the enable voltages. Truth Table Inputs OE H L L L L L L L L S2 X L L L L H H H H S1 X L L H H L L H H S0 X L H L H L H L H Z Z I0 I1 I2 I3.


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