74ABTH16841A

INTEGRATED CIRCUITS www.DataSheet4U.net 74ABT16841A 74ABTH16841A 20-bit bus interface latch (3-State) Product specification Supersedes data of 1995 Sep 28 IC23 Data Handbook 1998 Feb 27 Philips Semiconductors Philips Semiconductors Product specification 20-bit bus interface latch (3-State) 74ABT16841A 74ABTH16841A FEATURES High speed parallel latches Live insertion/extraction permitted Extra data width for wide address/data paths or buses carrying Power-up 3-State 74ABTH16841A incorporates bus-hold data inputs which eliminate the need for external pull-up resistors to hold unused inputs parity DESCRIPTION The 74ABT16841A Bus interface latch is designed to provide extra data width for wider data/address paths of buses carrying parity. The 74ABT16841A consists of two sets of ten D-type latches with 3-State outputs. The flip-flops appear transparent to the data when Latch Enable (nLE) is High. This allows asynchronous operation, as the output transition follows the data in transition. On the nLE High-to-Low transition, the data that meets the setup and hold time is latched. Data appears on the bus when the Output Enable (nOE) is Low. When nOE is High the output is in the High-impedance state. Two options are available, 74ABT16841A which does not have the bus-hold feature and 74ABTH16841A which incorporates the bus-hold feature. Power-up reset Ideal where high speed, light loading, or increased fan-in are Output capability: +64mA/–32mA Latch-up protec...