74ABT823

Philips Semiconductors 9-bit D-type flip-flop with reset and enable (3-State) Product specification 74ABT823 FEATURES High speed parallel registers with positive edge-triggered D-type flip-flops Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors Output capability: +64mA/–32mA Latch-up protection exceeds 500mA per Jedec Std 17 ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model Power-up 3-State Power-up Reset DESCRIPTION The 74ABT823 Bus interface Register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. The 74ABT823 is a 9-bit wide buffered register with Clock Enable (CE) and Master Reset (MR) which are ideal for parity bus interfacing in high microprogrammed systems. The register is fully edge-triggered. The state of each D input, one set-up time before the L...