7442

DM7442A BCD to Decimal Decoder August 1986 Revised February 2000 DM7442A BCD to Decimal Decoder General Description These BCD-to-decimal decoders consist of eight inverters and ten, four-input NAND gates. The inverters are connected in pairs to make BCD input data available for decoding by the NAND gates. Full decoding of input logic ensures that all outputs remain off for all invalid (10–15) input conditions. Features s Diode clamped inputs s Also for application as 4-line-to-16-line decoders; 3-line-to-8-line decoders s All outputs are high for invalid input conditions s Typical power dissipation 140 mW s Typical propagation delay 17 ns Ordering Code: Order Number DM7442AN Package Number N16E Package Description 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Connection Diagram © 2000 Fairchild Semiconductor Corporation DS006516 www.fairchildsemi.com DM7442A Function Table No. D 0 1 2 3 4 5 6 7 8 9 I N V A L I D H = HIGH Level L = LOW Level BCD Input C L L L L H H H H L L L L H H H H B L L H H L L H H L L H H L L H H A L H L H L H L H L H L H L H L H 0 L H H H H H H H H H H H H H H H 1 H L H H H H H H H H H H H H H H 2 H H L H H H H H H H H H H H H H 3 H H H L H H H H H H H H H H H H L L L L L L L L H H H H H H H H Decimal Output 4 H H H H L H H H H H H H H H H H 5 H H H H H L H H H H H H H H H H 6 H H H H H H L H H H H H H H H H 7 H H H H H H H L H H H H H H H H 8 H H H H H H H H L H H H H H H H 9 H H H H H H H H H L H H H H H H Logic Dia...