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IDT54FCT16841ET Dataheets PDF



Part Number IDT54FCT16841ET
Manufacturers Integrated Device Technology
Logo Integrated Device Technology
Description FAST CMOS 20-BIT TRANSPARENT LATCHES
Datasheet IDT54FCT16841ET DatasheetIDT54FCT16841ET Datasheet (PDF)

FAST CMOS 20-BIT TRANSPARENT LATCHES Integrated Device Technology, Inc. IDT54/74FCT16841AT/BT/CT/ET IDT54/74FCT162841AT/BT/CT/ET FEATURES: • Common features: – 0.5 MICRON CMOS Technology – High-speed, low-power CMOS replacement for ABT functions – Typical tSK(o) (Output Skew) < 250ps – Low input and output leakage ≤1µ A (max.) – ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) – Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP, 15.7 mil pitch TVSO.

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FAST CMOS 20-BIT TRANSPARENT LATCHES Integrated Device Technology, Inc. IDT54/74FCT16841AT/BT/CT/ET IDT54/74FCT162841AT/BT/CT/ET FEATURES: • Common features: – 0.5 MICRON CMOS Technology – High-speed, low-power CMOS replacement for ABT functions – Typical tSK(o) (Output Skew) < 250ps – Low input and output leakage ≤1µ A (max.) – ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) – Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack – Extended commercial range of -40°C to +85°C – VCC = 5V ±10% • Features for FCT16841AT/BT/CT/ET: – High drive outputs (-32mA IOH, 64mA IOL) – Power off disable outputs permit “live insertion” – Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V, TA = 25°C • Features for FCT162841AT/BT/CT/ET: – Balanced Output Drivers: ±24mA (commercial), ±16mA (military) – Reduced system switching noise – Typical VOLP (Output Ground Bounce) < 0.6V at VCC = 5V,TA = 25°C DESCRIPTION: The FCT16841AT/BT/CT/ET and FCT162841AT/BT/CT/ ET 20-bit transparent D-type latches are built using advanced dual metal CMOS technology. These high-speed, low-power latches are ideal for temporary storage of data. They can be used for implementing memory address latches, I/O ports, and bus drivers. The Output Enable and Latch Enable controls are organized to operate each device as two 10-bit latches or one 20-bit latch. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. The FCT16841AT/BT/CT/ET are ideally suited for driving high-capacitance loads and low-impedance backplanes. The output buffers are designed with power off disable capability to allow "live insertion" of boards when used as backplane drivers. The FCT162841AT/BT/CT/ET have balanced output drive with current limiting resistors. This offers low ground bounce, minimal undershoot, and controlled output fall times–reducing the need for external series terminating resistors. The FCT162841AT/BT/CT/ET are plug-in replacements for the FCT16841AT/BT/CT/ET and ABT16841 for on-board interface applications. FUNCTIONAL BLOCK DIAGRAM 1OE 2OE 1LE 1D1 2LE D 1Q1 2D1 D 2Q1 C C TO 9 OTHER CHANNELS 2556 drw 01 TO 9 OTHER CHANNELS 2556 drw 02 The IDT logo is a registered trademark of Integrated Device Technology, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES ©1996 Integrated Device Technology, Inc. JULY 1996 DSC-2556/7 5.18 1 IDT54/74FCT16841AT/BT/CT/ET, 162841AT/BT/CT/ET FAST CMOS 20-BIT TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATIONS 1OE 1Q1 1Q2 1 2 3 4 5 6 7 8 9 10 11 12 13 56 55 54 53 52 51 50 49 48 47 46 45 44 1LE 1D1 1D2 1OE 1Q1 1Q2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 CERPACK TOP VIEW E56-1 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 2556 drw 04 1LE 1D 1 1D 2 GND 1Q3 1Q4 GND 1D3 1D4 GND 1Q3 1Q4 G.


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