IDT54FCT16500ET

FAST CMOS 18-BIT REGISTERED TRANSCEIVER Integrated Device Technology, Inc. IDT54/74FCT16500AT/CT/ET IDT54/74FCT162500AT/CT/ET bit registered transceivers are built using advanced dual metal CMOS technology. These high-speed, low-power 18-bit reg Common features: istered bus transceivers combine D-type latches and D-type – 0.5 MICRON CMOS Technology flip-flops to allow data flow in transparent, latched and clocked – High-speed, low-power CMOS replacement for modes. Data flow in each direction is controlled by outputABT functions enable (OEAB and OEBA), latch enable (LEAB and LEBA) – Typical tSK(o) (Output Skew) < 250ps and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, – Low input and output leakage ≤1µ A (max.) the device operates in transparent mode when LEAB is HIGH. – ESD > 2000V per MIL-STD-883, Method 3015; When LEAB is LOW, the A data is latched if CLKAB is held at > 200V using machine model (C = 200pF, R = 0) a HIGH or LOW logic level. If LEAB is LOW, the A bus data is – Packages include 25 mil pitch SSOP, 19.6 mil pitch stored in the latch/flip-flop on the HIGH-to-LOW transition of TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack CLKAB . OEAB performs the output enable function on the B – Extended commercial range of -40°C to +85°C port. Data flow from B port to A port is similar but uses OEBA, – VCC = 5V ±10% LEBA and CLKBA . Flow-through organization of signal pins Features for FCT16500AT/CT/ET: simplifies layout. All inputs are designed with hystere...