Document
FAST CMOS 18-BIT REGISTER
Integrated Device Technology, Inc.
IDT54/74FCT16823AT/BT/CT/ET IDT54/74FCT162823AT/BT/CT/ET
FEATURES:
• Common features: – 0.5 MICRON CMOS Technology – High-speed, low-power CMOS replacement for ABT functions – Typical tSK(o) (Output Skew) < 250ps – Low input and output leakage ≤1µ A (max.) – ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) – Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack – Extended commercial range of -40°C to +85°C – VCC = 5V ±10% • Features for FCT16823AT/BT/CT/ET: – High drive outputs (-32mA IOH, 64mA IOL) – Power off disable outputs permit “live insertion” – Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V, TA = 25°C • Features for FCT162823AT/BT/CT/ET: – Balanced Output Drivers: ±24mA (commercial), ±16mA (military) – Reduced system switching noise – Typical VOLP (Output Ground Bounce) < 0.6V at VCC = 5V,TA = 25°C
DESCRIPTION:
The FCT16823AT/BT/CT/ET and FCT162823AT/BT/CT/ ET 18-bit bus interface registers are built using advanced, dual metal CMOS technology. These high-speed, low-power registers with clock enable (xCLKEN) and clear (xCLR) controls are ideal for parity bus interfacing in high-performance synchronous systems. The control inputs are organized to operate the device as two 9-bit registers or one 18-bit register. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. The FCT16823AT/BT/CT/ET are ideally suited for driving high-capacitance loads and low-impedance backplanes. The output buffers are designed with power off disable capability to allow "live insertion" of boards when used as backplane drivers. The FCT162823AT/BT/CT/ET have balanced output drive with current limiting resistors. This offers low ground bounce, minimal undershoot, and controlled output fall times – reducing the need for external series terminating resistors. The FCT162823AT/BT/CT/ET are plug-in replacements for the FCT16823AT/BT/CT/ET and ABT16823 for on-board interface applications.
FUNCTIONAL BLOCK DIAGRAM
1OE 1CLR 1CLK 1CLKEN
2OE 2CLR 2CLK 2CLKEN
R C D 1D1
1Q1 2D1
R C D
2Q1
TO 8 OTHER CHANNELS
2772 drw 01
TO 8 OTHER CHANNELS
2772 drw 02
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
AUGUST 1996
DSC-2772/8
5.16
1
IDT54/74FCT16823AT/BT/CT/ET, 162823AT/BT/CT/ET FAST CMOS 18-BIT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
1CLR 1OE 1Q1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 SO56-1 43 SO56-2 SO56-3 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1CLK 1CLKEN 1D1
1CLR 1OE 1Q1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 CERPACK TOP VIEW E56-1
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1CLK 1CLKEN 1D1
GND
1Q2 1Q3
GND
1D2 1D3
GND
1Q2 1Q3
GND
1D2 1D3
VCC
1Q4 1Q5 1Q6
VCC
1D4 1D5 1D6
VCC
1Q4 1Q5 1Q6
VCC
1D4 1D5 1D6
GND
1Q7 1Q8 1Q9 2Q1 2Q2 2Q3
GND
1D7 1D8 1D9 2D1 2D2 2D3
GND
1Q7 1Q8 1Q9 2Q1 2Q2 2Q3
GND
1D7 1D8 1D9 2D1 2D2 2D3
GND
2Q4 2Q5 2Q6
GND
2D4 2D5 2D6
GND
2Q4 2Q5 2Q6
GND
2D4 2D5 2D6
VCC
2Q7 2Q8
VCC
2D7 2D8
VCC
2Q7 2Q8
VCC
2D7 2D8
GND
2Q9 2OE 2CLR
GND
2D9 2CLKEN 2CLK
GND
2Q9 2OE 2CLR
GND
2D9 2CLKEN 2CLK
SSOP/ TSSOP/TVSOP TOP VIEW
2772 drw 03
2772 drw 04
5.16
2
IDT54/74FCT16823AT/BT/CT/ET, 162823AT/BT/CT/ET FAST CMOS 18-BIT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Names xDx xCLK xCLKEN xCLR xOE xQx Description Data inputs Clock Inputs Clock Enable Inputs (Active LOW) Asynchronous clear Inputs (Active LOW) Output Enable Inputs (Active LOW) 3-State Outputs
2772 tbl 01
FUNCTION TABLE(1)
xOE H L L H H L L xCLR X L H H H H H Inputs xCLKEN X X H L L L L xCLK X X X ↑ ↑ ↑ ↑ xDx X X X L H L H Outputs xQx Function Z L Q(2) Z Z L H High Z Clear Hold Load
ABSOLUTE MAXIMUM RATINGS
(1)
Unit V V °C mA
Symbol Description Max. VTERM(2) Terminal Voltage with Respect to –0.5 to +7.0 GND VTERM(3) Terminal Voltage with Respect to –0.5 to GND VCC +0.5 TSTG Storage Temperature –65 to +150 I OUT DC Output Current –60 to +120
NOTES: 2772 tbl 02 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance 2. Output level before indicated steady-state input conditions were established.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter(1) CIN Input Capacitance COUT Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 3.5 3.5 Max. Unit 6.0 pF 8.0
pF
2772 lnk 03 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifi.