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74F114

Fairchild Semiconductor

Dual JK Negative Edge-Triggered Flip-Flop


Description
74F114 Dual JK Negative Edge-Triggered Flip-Flop April 1988 Revised August 1999 74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears General Description The 74F114 contains two high-speed JK flip-flops with common Clock and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at...



Fairchild Semiconductor

74F114

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