74F109

74F109 Dual JK Positive Edge-Triggered Flip-Flop April 1988 Revised November 1999 74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J and K inputs. Asynchronous Inputs: LOW input to SD sets Q to HIGH level LOW input to CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH Ordering Code: Order Number 74F109SC 74F109SJ 74F109PC Package Number M16A M16D N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body 16-Lead Small Outline Package (SOP), EIAJ TYPE 11, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 1999 Fairchild Semiconductor Corporation DS009471 www.fairchildsemi.com 74F109 Truth Table Inputs SD L H L H H H H H CD H L L H H H H H CP X X J X X X I h I h X K X X X I I h h X Q H Q Q H L H L Toggle Q L Q Outputs Q L H H H     X L H (h) = HIGH Voltage Level L (l) = LOW Voltage Level = LOW-to-HIGH Transition X = Immaterial Q0 (Q0) = Before LOW-to-HIGH Transition of Clock Lower case ...