74ALVT16899

INTEGRATED CIRCUITS 74ALVT16899 2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State) Product specification IC23 Data Handbook 1998 Jun 30 Philips Semiconductors Philips Semiconductors Product specification 2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 74ALVT16899 FEATURES Symmetrical (A and B bus functions are identical) Selectable generate parity or ”feed-through” parity for A-to-B and B-to-A directions can generate or check parity. The parity bit can be fed-through with no change or the generated parity can be substituted with the SEL input. The 74ALVT16899 features independent latch enables for the A and B bus latches, a select pin for ODD/EVEN parity, and separate error signal output pins for checking parity. Independent transparent latches for A-to-B and B-to-A directions Selectable ODD/EVEN parity Continuously checks parity of both A bus and B bus latches as ERRA and ERRB FUNCTIONAL DESCRIPTION: The 74ALVT16899 has three principal modes of operation which are outlined below. All modes apply to both the A-to-B and B-to-A directions. Transparent latch, Generate parity, Check A and B bus parity: Bus A (B) communicates to Bus B (A), parity is generated and passed on to the B (A) Bus as BPAR (APAR). If LEA and LEB are High and the Mode Select (SEL) is Low, the parity generated from A0-A7 and B0-B7 can be checked and monitored by ERRA and ERRB. (Fault detection on both input and output b...