DatasheetsPDF.com

74ALS273 Dataheets PDF



Part Number 74ALS273
Manufacturers NXP
Logo NXP
Description Octal D-type flip-flop
Datasheet 74ALS273 Datasheet74ALS273 Datasheet (PDF)

INTEGRATED CIRCUITS 74ALS273 Octal D–type flip–flop Product specification IC05 Data Handbook 1991 Feb 08 Philips Semiconductors Philips Semiconductors Product specification Octal D-type flip-flop 74ALS273 FEATURES • Eight edge-triggered D-type flip-flops • Buffered common clock • Buffered asynchronous master reset • See 74ALS377 for clock enable version • See 74ALS373 for transparent latch version • See 74ALS374 for 3-State version DESCRIPTION The 74ALS273 has eight edge-triggered D-type.

  74ALS273   74ALS273



Document
INTEGRATED CIRCUITS 74ALS273 Octal D–type flip–flop Product specification IC05 Data Handbook 1991 Feb 08 Philips Semiconductors Philips Semiconductors Product specification Octal D-type flip-flop 74ALS273 FEATURES • Eight edge-triggered D-type flip-flops • Buffered common clock • Buffered asynchronous master reset • See 74ALS377 for clock enable version • See 74ALS373 for transparent latch version • See 74ALS374 for 3-State version DESCRIPTION The 74ALS273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition, is transferred to the corresponding flip-flop’s Q output. All outputs will be forced Low independently of clock or data inputs by a Low voltage level on the MR input. The device is useful for applications where the true output only is required and the CP and MR are common to all flip-flops. TYPICAL SUPPLY CURRENT (TOTAL) 16mA PIN CONFIGURATION MR Q0 D0 D1 Q1 Q2 D2 D3 Q3 1 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 11 VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CP GND 10 SF00346 ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 74ALS273N 74ALS273D 74ALS273DB DRAWING NUMBER 20-pin plastic DIP 20-pin plastic SO 20-pin plastic SSOP Type II SOT146-1 SOT163-1 SOT339-1 TYPE 74ALS273 TYPICAL fMAX 95MHz INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS D0 – D7 CP MR Q0 – Q7 Data inputs Clock pulse input (active rising edge) Master Reset input (active-Low) 3-State outputs DESCRIPTION 74ALS (U.L.) HIGH/LOW 1.0/2.0 1.0/1.0 1.0/1.0 130/240 LOAD VALUE HIGH/LOW 20µA/0.2mA 20µA/0.1mA 20µA/0.1mA 2.6mA/24mA NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state. LOGIC SYMBOL 3 4 7 8 13 14 17 18 IEC/IEEE SYMBOL 1 11 R C1 D0 11 1 CP MR D1 D2 D3 D4 D5 D6 D7 3 4 7 1D 2 5 6 9 12 15 16 19 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 8 13 14 2 VCC = Pin 20 GND = Pin 10 5 6 9 12 15 16 19 17 18 SF00347 SF00348 1991 Feb 08 2 853–1398 01670 Philips Semiconductors Product specification Octal D-type flip-flop 74ALS273 LOGIC DIAGRAM D0 3 CP 11 D1 4 D2 7 D3 8 D4 13 D5 14 D6 17 D7 18 D Q D Q D Q D Q D Q D Q D Q D Q CP RD MR 1 CP RD CP RD CP RD CP RD CP RD CP RD CP RD 2 Q0 VCC = Pin 20 GND = Pin 10 Q1 5 Q2 6 Q3 9 12 Q4 15 Q5 16 Q6 19 Q7 SF00349 FUNCTION TABLE INPUTS MR L H H H h L l X ↑ = = = = = = CP X ↑ ↑ Dn X h l OUTPUTS Qn L H L Reset (clear) Load “1” Load “0” OPERATING MODE High-voltage level High state must be present one setup time before the Low-to-High clock transition Low-voltage level Low state must be present one setup time before the Low-to-High clock transition Don’t care Low-to-High clock transition ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this tabl.


74ALS27 74ALS273 74ALS30A


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)