74ALS163B

INTEGRATED CIRCUITS 74ALS161B/74ALS163B 4-bit binary counter Product specification IC05 Data Handbook 1991 Feb 08 Philips Semiconductors Philips Semiconductors Product specification 4-bit binary counter 74ALS161B 74ALS163B FEATURES 74ALS161B/74ALS163B 4-bit binary counter, asynchronous reset 4-bit binary counter, synchronous reset DESCRIPTION Synchronous presettable 4-bit binary counters (74ALS161B, 74ALS163B) feature an internal carry look-ahead and can be used for high speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock. The clock input is buffered. The outputs of the counters may be preset to High or Low level. A Low level at the parallel enable (PE) input disables the counting action and causes the data at the D0 – D3 inputs to be loaded into the counter on the positive-going edge of the clock (provided that the setup and hold requirements for PE are met). Preset takes place regardless of the levels at count enable (CEP, CET) inputs. A Low level at the master reset (MR) input sets all the four outputs of the flip-flops (Q0 – Q3) in 74ALS161B to Low levels, regardless of the levels at CP, PE, CET and CEP inputs (thus providing an asynchronous clear function). For the 74ALS163B the clear function is synchronous. A Low level at the synchronous reset (SR) input sets all four outputs of the flip-flops (Q0 – Q3) to Low levels after the next positive-going transition on the clock (CP) in...