74AHCT86

INTEGRATED CIRCUITS DATA SHEET 74AHC86; 74AHCT86 Quad 2-input EXCLUSIVE-OR gate Product specification File under Integrated Circuits, IC06 1999 Sep 17 Philips Semiconductors Product specification Quad 2-input EXCLUSIVE-OR gate FEATURES ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V Inputs accepts voltages higher than VCC For AHC only: operates with CMOS input levels For AHCT only: operates with TTL input levels Specified from −40 to +85 °C and −40 to +125 °C. DESCRIPTION The 74AHC/AHCT86 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74AHC/AHCT86 provides the 2-input EXCLUSIVE-OR function. 74AHC86; 74AHCT86 QUICK REFERENCE DATA Ground = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns. TYPICAL SYMBOL tPHL/tPLH CI CO CPD PARAMETER propagation delay nA, nB to nY input capacitance power dissipation capacitance CONDITIONS AHC CL = 15 pF; VCC = 5 V VI = VCC or GND CL = 50 pF; f = 1 MHz; notes 1 and 2 3.4 3.0 4.0 10 AHCT 3.4 3.0 4.0 12 ns pF pF pF UNIT output capacitance VI = VCC or GND Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; ∑ (CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition is VI...