74AHC138

INTEGRATED CIRCUITS DATA SHEET 74AHC138; 74AHCT138 3-to-8 line decoder/demultiplexer; inverting Product specification Supersedes data of 1999 Mar 31 File under Integrated Circuits, IC06 1999 Sep 27 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer; inverting FEATURES ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V Balanced propagation delays All inputs have Schmitt-trigger actions Multiple input enable for easy expansion Ideal for memory chip select decoding Inputs accept voltages higher than VCC For AHC only: operates with CMOS input levels For AHCT only: operates with TTL input levels Specified from −40 to +85 and +125 °C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns. DESCRIPTION 74AHC138; 74AHCT138 The 74AHC/AHCT138 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT138 decoders accept three binary weighted address inputs (A0, A1 and A2) and when enabled, provide 8 mutually exclusive active LOW outputs (Y0 to Y7). The ‘138’ features three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the ‘138’ to a 1-of-32 (5 to 32 lines) decoder with just four ‘138’ ICs and one ...