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74ACT373 Dataheets PDF



Part Number 74ACT373
Manufacturers STMicroelectronics
Logo STMicroelectronics
Description OCTAL D-TYPE LATCH
Datasheet 74ACT373 Datasheet74ACT373 Datasheet (PDF)

74ACT373 OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING s s s s s s s s s HIGH SPEED: tPD = 6 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 8 µA (MAX.) at TA = 25 oC COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN), VIL = 0.8V (MAX) 50Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373 IMPROVED LATCH-UP I.

  74ACT373   74ACT373



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74ACT373 OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING s s s s s s s s s HIGH SPEED: tPD = 6 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 8 µA (MAX.) at TA = 25 oC COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN), VIL = 0.8V (MAX) 50Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373 IMPROVED LATCH-UP IMMUNITY B M (Plastic Package) (Micro Package) ORDER CODES : 74ACT373B 74ACT373M (OE). While the LE inputs is held at a high level, the Q outputs will follow the data input precisely or inversely. When the LE is taken low, the Q outputs will be latched precisely or inversely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. This device is designed to interface directly High Speed CMOS systems with TTL and NMOS components. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. DESCRIPTION The ACT373 is an advanced high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power applications mantaining high speed operation similar to equivalent Bipolar Schottky TTL. These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input PIN CONNECTION AND IEC LOGIC SYMBOLS April 1997 1/10 74ACT373 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 11 10 20 SYMBOL OE Q0 to Q7 NAME AND F UNCTIO N 3 State Output Enable Input (Active LOW) Data Inputs D0 to D7 3 State Outputs LE GND VCC Latch Enable Input Ground (0V) Positive Supply Voltage TRUTH TABLE INPUT S OE H L L L LE X L H H D X X L H OUT PUT S Q Z NO CHANGE * L H X: DON’T CARE Z: HIGH IMPEDANCE *: Q OUTPUTS ARE LATCHED AT THE TIME WHEN THE LE INPUT IS TAKEN LOW LOGIC LEVEL. LOGIC DIAGRAMS 2/10 74ACT373 ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 ± 20 ± 20 ± 50 ± 400 -65 to +150 300 Unit V V V mA mA mA mA o o ICC or IGND DC VCC or Ground Current C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO Top dt/dv Supply Voltage Input Voltage Output Voltage Operating Temperature: Input Rise and Fall Time VCC = 4.5 to 5.5V (note 1) Parameter Valu e 4.5 to 5.5 0 to VCC 0 to .


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