DSP56F802 16-bit Digital Signal Processor
DSP56F802/D Rev. 0, 1/2002
DSP56F802
Preliminary Technical Data
DSP56F802 16-bit Digital Signal Processor
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Description
DSP56F802/D Rev. 0, 1/2002
DSP56F802
Preliminary Technical Data
DSP56F802 16-bit Digital Signal Processor
Up to 40 MIPS operation at 80 MHz core frequency DSP and MCU functionality in a unified, C-efficient architecture MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes 8K × 16-bit words Program Flash 1K × 16-bit words Program RAM 2K × 16-bit words Data Flash 1K × 16-bit words Data RAM 2K × 16-bit words Boot Flash Hardware DO and REP loops 6-channel PWM Module with fault input Two 12-bit ADCs (1 x 2 channel, 1 x 3 channel) Serial Communications Interface (SCI) Two General Purpose Quad Timers with 2 external outputs JTAG/OnCETM port for debugging 4 shared GPIO On-chip relaxation oscillator 32-pin LQFP Package
6
PWM Outputs Fault A0
PWMA
RESET 5 JTAG/ OnCE Port VCAPC VDD 2 2 3 Digital Reg Analog Reg VSS* VDDA VSSA
2 3
A/D1 A/D2 VREF
ADC Interrupt Controller
Low Voltage Supervisor
Program Controller and Hardware Looping Unit
Address Generation Unit
Data ALU 16 x 16 + 36 → 36-Bit MAC Three 16-bit Input Registers Two 36-bit Accumulators
Bit Manipulation Unit
Quad Timer C Quad Timer D or GPIO
Program Memory 8188 x 16 Flash 1024 x 16 SRAM Boot Flash 2048x 16 Flash Data Memory 2048 x 16 Flash 1024 x 16 SRAM
PAB
PDB
IPBB CONTROLS 16 Relaxation Oscillator
PLL
2
XDB2 CGDB XAB1 XAB2
.
2
SCI0 or GPIO
INTERRUPT CONTROLS 16 COP/ Watchdog COP RE...
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