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4X16E43V Dataheets PDF



Part Number 4X16E43V
Manufacturers ETC
Logo ETC
Description 4 MEG x 16 EDO DRAM
Datasheet 4X16E43V Datasheet4X16E43V Datasheet (PDF)

4 MEG x 16 EDO DRAM EDO DRAM FEATURES • Single +3.3V ±0.3V power supply • Industry-standard x16 pinout, timing, functions, and package • 12 row, 10 column addresses (4) 13 row, 9 column addresses (8) • High-performance CMOS silicon-gate process • All inputs, outputs and clocks are LVTTL-compatible • Extended Data-Out (EDO) PAGE MODE access • 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH distributed across 64ms • Self refresh for low-power data retention 4X16E43V PIN ASSIGNMENT (Top View) 50-Pin .

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4 MEG x 16 EDO DRAM EDO DRAM FEATURES • Single +3.3V ±0.3V power supply • Industry-standard x16 pinout, timing, functions, and package • 12 row, 10 column addresses (4) 13 row, 9 column addresses (8) • High-performance CMOS silicon-gate process • All inputs, outputs and clocks are LVTTL-compatible • Extended Data-Out (EDO) PAGE MODE access • 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH distributed across 64ms • Self refresh for low-power data retention 4X16E43V PIN ASSIGNMENT (Top View) 50-Pin TSOP VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 NC VCC WE# RAS# NC NC NC NC A0 A1 A2 A3 A4 A5 VCC †A12 OPTIONS • Plastic Package 50-pin TSOP (400 mil) • Timing 50ns access 60ns access • Refresh Rates 4K 8K • Operating Temperature Range Commercial (0°C to +70°C) Extended (-40°C to +85°C) MARKING TW -5 -6 4 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 NC VSS CASL# CASH# OE# NC NC NC/A12† A11 A10 A9 A8 A7 A6 VSS for "8K" version, NC for "4K" version. 4X16E43V 4X16E83V None IT Configuration Refresh Row Address Column Addressing 4 Meg x 16 4K 4K (A0-A11) 1K (A0-A9) 4 Meg x 16 8K 8K (A0-A12) 512 (A0-A8) NOTE: 1. The “#” symbol indicates signal is active LOW. 4 MEG x 16 EDO DRAM PART NUMBERS Part Number Example: MEM4X16E43VTW-5 PART NUMBER 4X16E43VTW-x 4X16E83VTW-x tCAC tCAS REFRESH ADDRESSING 4 8 PACKAGE 400-TSOP 400-TSOP KEY TIMING PARAMETERS SPEED -5 -6 tRC 84ns 104ns tRAC 50ns 60ns tPC 20ns 25ns tAA 25ns 30ns 13ns 15ns 8ns 10ns x = speed 1 4 MEG x 16 EDO DRAM FUNCTIONAL BLOCK DIAGRAM 4X16E43V (12 row addresses) WE# CASL# CASH# CAS# DATA-IN BUFFER 16 DQ0DQ15 NO. 2 CLOCK GENERATOR DATA-OUT BUFFER 16 OE# 16 10 COLUMNADDRESS BUFFER(10) REFRESH CONTROLLER 16 10 COLUMN DECODER 1,024 SENSE AMPLIFIERS I/O GATING 1,024 x 16 A0A11 REFRESH COUNTER ROW SELECT 12 12 ROWADDRESS BUFFERS (12) ROW DECODER COMPLEMENT SELECT 12 4,096 4,096 x 16 4,096 x 1,024 x 16 MEMORY ARRAY RAS# NO. 1 CLOCK GENERATOR VDD VSS FUNCTIONAL BLOCK DIAGRAM 4X16E83V (13 row addresses) WE# CASL# CASH# CAS# DATA-IN BUFFER 16 DQ0DQ15 NO. 2 CLOCK GENERATOR DATA-OUT BUFFER 16 OE# 16 9 COLUMNADDRESS BUFFER(9) REFRESH CONTROLLER 16 9 COLUMN DECODER 512 SENSE AMPLIFIERS I/O GATING 512 x 16 A0A12 REFRESH COUNTER ROW SELECT 13 13 ROWADDRESS BUFFERS (13) COMPLEMENT SELECT ROW DECODER 13 8192 8192 x 16 8192 x 512 x 16 MEMORY ARRAY RAS# NO. 1 CLOCK GENERATOR Vcc Vss 2 4 MEG x 16 EDO DRAM GENERAL DESCRIPTION The 4 Meg x 16 DRAM is a high-speed CMOS, dynamic random-access memory device containing 67,108,864 bits and designed to operate from 3V to 3.6V. The device is functionally organized as 4,194,304 locations containing 16 bits each. The 4,194,304 memory locations are arranged in 4,096 rows by 1,024 columns on the MEM4X16E43VTW. During READ or WRITE cycles, each location is uniquely addressed via the address bits: 12 row-address bits (A0-A11) and 10 column-address bits (A0-A9) on the MEM4X16E43VTW version. In addition, the byte and word accesses are supported via the two CAS# pins (CASL# and CASH#). The CAS# functionality and timing related to address and control functions (e.g., latching column addresses or selecting CBR REFRESH) is such that the internal CAS# signal is determined by the first external CAS# signal (CASL# or CASH#) to transition LOW and the last to transition back HIGH. The CAS# functionality and timing related to driving or latching data is such that each CAS# signal independently controls the associated eight DQ pins. The row address is latched by the RAS# signal, then the column address is latched by CAS#. This device provides EDO-PAGE-MODE operation, allowing for fast successive data operations (READ, WRITE or READMODIFY-WRITE) within a given row. The 4 Meg x 16 DRAM must be refreshed periodically in order to retain stored data. DRAM ACCESS Each location in the DRAM is uniquely addressable, as mentioned in the General Description. Use of both CAS# signals results in a word access via the 16 I/O pins (DQ0-DQ15). Using only one of the two signals results in a BYTE access cycle. CASL# transitioning LOW selects an access cycle for the lower byte (DQ0-DQ7), and CASH# transitioning LOW selects an access cycle for WORD WRITE RAS# LOWER BYTE WRITE CASL# CASH# WE# LOWER BYTE (DQ0-DQ7) OF WORD STORED DATA 1 1 0 1 1 1 1 1 INPUT DATA 0 0 1 0 0 0 0 0 INPUT DATA STORED DATA 0 0 1 0 0 0 0 0 STORED DATA 0 0 1 0 0 0 0 0 INPUT DATA 1 1 0 1 1 1 1 1 INPUT DATA STORED DATA 1 1 0 1 1 1 1 1 UPPER BYTE (DQ8-DQ15) OF WORD 0 1 0 1 0 0 0 0 X X X X X X X X ADDRESS 0 1 0 1 0 1 1 1 1 1 0 1 0 1 1 1 1 1 0 1 0 1 1 1 1 X X X X X X X X ADDRESS 1 1 0 1 0 1 1 1 1 X = NOT EFFECTIVE (DON?T CARE) Figure 1 WORD and BYTE WRITE Example 3 4 MEG x 16 EDO DRAM DRAM ACCESS (continued) the upper byte (DQ8-DQ15). General byte and word access timing is shown i.


4R3TI60Y-080 4X16E43V 4X16E83V


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