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42S32200 Dataheets PDF



Part Number 42S32200
Manufacturers ETC
Logo ETC
Description 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
Datasheet 42S32200 Datasheet42S32200 Datasheet (PDF)

IS42S32200 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM FEATURES • Clock frequency: 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single 3.3V power supply • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burst sequence: Sequential/Interleave • Self refresh modes • 4096 refresh cycles every 64 ms • Random column address every clock cycle • Programmable CAS.

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IS42S32200 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM FEATURES • Clock frequency: 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single 3.3V power supply • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burst sequence: Sequential/Interleave • Self refresh modes • 4096 refresh cycles every 64 ms • Random column address every clock cycle • Programmable CAS latency (2, 3 clocks) • Burst read/write and burst read/single write operations capability • Burst termination by burst stop and precharge command • Industrial temperature availability • Package 400-mil 86-pin TSOP II ISSI PIN CONFIGURATION (86-Pin TSOP (Type II) ® PRELIMINARY INFORMATION August 2003 OVERVIEW ISSI's 64Mb Synchronous DRAM IS42S32200 is organized as 524,288 bits x 32-bit x 4-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. VCC I/O0 VCCQ I/O1 I/O2 GNDQ I/O3 I/O4 VCCQ I/O5 I/O6 GNDQ I/O7 NC VCC DQM0 WE CAS RAS CS NC BA0 BA1 A10/AP A0 A1 A2 DQM2 VCC NC I/O16 GNDQ I/O17 I/O18 VCCQ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 GND I/O15 GNDQ I/O14 I/O13 VCCQ I/O12 I/O11 GNDQ I/O10 I/O9 VCCQ I/O8 NC GND DQM1 NC NC CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 GND NC I/O31 VCCQ I/O30 I/O29 GNDQ I/O28 I/O27 VCCQ I/O26 I/O25 GNDQ I/O24 GND PIN DESCRIPTIONS A0-A10 BA0, BA1 I/O0 to I/O31 CLK CKE CS RAS CAS WE Address Input Bank Select Address Data I/O System Clock Input Clock Enable Chip Select Row Address Strobe Command Column Address Strobe Command Write Enable I/O19 I/O20 GNDQ I/O21 I/O22 VCCQ I/O23 VCC Vcc GND VccQ GNDQ NC Power Ground Power Supply for I/O Pin Ground for I/O Pin No Connection DQM0 to DQM3 Input/Output Mask Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION 08/14/03 Rev. 00B 1 IS42S32200 GENERAL DESCRIPTION The 64Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V memory systems containing 67,108,864 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 16,777,216-bit bank is organized as 2,048 rows by 256 columns by 32 bits. The 64Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible. The 64Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access. A self-timed row precharge initiated at the end of the burst sequence is available with the AUTO PRECHARGE ISSI ® function enabled. Precharge one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. SDRAM read and write accesses are burst oriented starting at a selected location and continuing for a programmed number of locations in a programmed sequence. The registration of an ACTIVE command begins accesses, followed by a READ or WRITE command. The ACTIVE command in conjunction with address bits registered are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A10 select the row). The READ or WRITE commands in conjunction with address bits registered are used to select the starting column location for the burst access. Programmable READ or WRITE burst lengths consist of 1, 2, 4 and 8 locations or full page, with a burst terminate option. FUNCTIONAL BLOCK DIAGRAM CLK CKE CS RAS CAS WE DQM0-3 COMMAND DECODER & CLOCK GENERATOR DATA IN BUFFER 32 32 MODE REGISTER 10 REFRESH CONTROLLER I/O 0-31 SELF REFRESH CONTROLLER A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BA0 BA1 10 DATA OUT BUFFER 32 32 Vcc/VccQ GND/GNDQ REFRESH COUNTER 2048 2048 2048 2048 ROW DECODER MULTIPLEXER MEMORY CELL ARRAY 10 ROW ADDRESS LATCH 10 ROW ADDRESS BUFFER BANK 0 SENSE AMP I/O GATE COLUMN ADDRESS LATCH 256 (x 32) BANK CONTROL LOGIC BURST COUNTER COLUMN DECODER COLUMN ADDRESS BUFFER 2 Integrated Silicon .


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