VDSL Wireline Simulator
The DLS 8100 is Spirent Communications DLS Systems latest wireline
simulator. Designed specifically for testing VDSL equipment up to 30 MHz,
the DLS 8100 is the only product on the market capable of providing the
necessary bandwidth, along with full simulation of propagation delay,
phase and attenuation effects.
Delivering high-speed data, voice and video to a subscriber over a single pair of wires
requires pushing the limits both of circuit design and algorithms for data compression,
error correction, and echo cancellation. You can test these features, and more, with the
DLS 8100. To ensure that your test data carries the weight it deserves, the DLS 8100, as
with all DLS Systems simulators, is compliant to national and international standards.
The DLS 8100 combines simulation of the DC path and the VDSL signal path. The unit is
fully bi-directional, with all cable characteristics being accurately simulated. Using a unique
circuit design, the DLS 8100 realistically simulates real cable without the inherent limitations
of digital signal processing. The DLS 8100 reproduces all balanced impedance, propagation
delay, phase, and attenuation effects, giving you precise, accurate testing for all your
applications. The unit has been designed to ensure that the effects of bridged taps,
mismatches, and reflections are all present.
In designing the architecture of the DLS 8100, DLS Systems has applied the experience
acquired from 15 years in the simulation industry. You get a solid test platform from a
company you can trust to deliver the very best.
The DLS 8100 control software is PC based and links the PC to the DLS 8100 via an IEEE 488
or RS-232C interface. With easy to read visuals and pull down menus, the DLS 8100 software
makes setting up a desired loop quick and easy.
The DLS 8100 simulates the VDSL0 or Null loop, VDSL1 loop, and the VDSL1 loop with
bridged tap in conformance to the ANSI Draft Technical Report on System Requirements
for VDSL (VDSL SR:98-043R6).
Loop VDSL0, or null loop, uses relays to create a zero length loop allowing the performance
of the null test.