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EBS21RC2ACNA Dataheets PDF



Part Number EBS21RC2ACNA
Manufacturers Elpida Memory
Logo Elpida Memory
Description 2GB Registered SDRAM DIMM
Datasheet EBS21RC2ACNA DatasheetEBS21RC2ACNA Datasheet (PDF)

DATA SHEET 2GB Registered SDRAM DIMM EBS21RC2ACNA (256M words × 72 bits, 2 banks) Description The EBS21RC2ACNA is 256M words × 72 bits, 2 banks Synchronous Dynamic RAM Registered Module, mounted 72 pieces of 256M bits SDRAM sealed in TCP package. This module provides high density and large quantities of memory in a small space without utilizing the surface mounting technology. Decoupling capacitors are mounted on power supply line for noise reduction. Note: Do not push the cover or drop the mod.

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DATA SHEET 2GB Registered SDRAM DIMM EBS21RC2ACNA (256M words × 72 bits, 2 banks) Description The EBS21RC2ACNA is 256M words × 72 bits, 2 banks Synchronous Dynamic RAM Registered Module, mounted 72 pieces of 256M bits SDRAM sealed in TCP package. This module provides high density and large quantities of memory in a small space without utilizing the surface mounting technology. Decoupling capacitors are mounted on power supply line for noise reduction. Note: Do not push the cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. Features • Fully compatible with 8 bytes DIMM: JEDEC standard outline • 168-pin socket type dual in line memory module (DIMM)  PCB height: 41.91mm (1.65inch )  Lead pitch: 1.27mm • 3.3V power supply • Clock frequency: 133MHz (max.) • LVTTL interface • Data bus width: × 72 ECC • Single pulsed /RAS • 4 Banks can operates simultaneously and independently • Burst read/write operation and burst read/single write operation capability • Programmable burst length (BL): 1, 2, 4, 8 • 2 variations of burst sequence  Sequential  Interleave • Programmable /CAS latency (CL): 2, 3 • Registered inputs with one clock delay • Byte control by DQMB • Refresh cycles: 8192 refresh cycles/64ms • 2 variations of refresh  Auto refresh  Self refresh • 1 piece of PLL clock driver, 3 pieces of register driver and 1 piece of serial EEPROM (2k bits) for Presence Detect (SPD) on PCB. Document No. E0105E50 (Ver. 5.0) Date Published June 2002 (K) Japan URL: http://www.elpida.com Elpida Memory, Inc. 2001-2002 EBS21RC2ACNA Ordering Information Part number EBS21RC2ACNA-7A EBS21RC2ACNA-75*1 Clock frequency MHz (max.) 133 133 /CAS latency 2, 3 3 Package 168-pin DIMM Contact pad Gold Mounted devices 256M bits SDRAM TCP*2 Note: 1. 100MHz operation at /CAS latency = 2. 2. Please refer to the TSOP products EDS25XXACTA datasheet (E0277E) for detail information. Pin Configurations 1 pin 10 pin 11 pin 40 pin 41 pin 84 pin 85 pin 94 pin 95 pin 124 pin 125 pin 168 pin Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Pin name VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 CB0 CB1 VSS NC NC VDD /WE DQMB0 DQMB1 Pin No. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 Pin name VSS NC /CS2 DQMB2 DQMB3 NC VDD NC NC CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 VDD DQ20 NC NC NC VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 Pin No. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 Pin name VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 CB4 CB5 VSS NC NC VDD /CAS DQMB4 DQMB5 Pin No. 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 Pin name VSS CKE0 /CS3 DQMB6 DQMB7 NC VDD NC NC CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VDD DQ52 NC NC REGE VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 Data Sheet E0105E50 (Ver. 5.0) 2 EBS21RC2ACNA Pin No. 30 31 32 33 34 35 36 37 38 39 40 41 42 Pin name /CS0 NC VSS A0 A2 A4 A6 A8 A10 (AP) BA1 VDD VDD CLK0 Pin No. 72 73 74 75 76 77 78 79 80 81 82 83 84 Pin name DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS CLK2 NC NC SDA SCL VDD Pin No. 114 115 116 117 118 119 120 121 122 123 124 125 126 Pin name /CS1 /RAS VSS A1 A3 A5 A7 A9 BA0 A11 VDD CLK1 A12 Pin No. 156 157 158 159 160 161 162 163 164 165 166 167 168 Pin name DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS CLK3 NC SA0 SA1 SA2 VDD Pin Description Pin name A0 to A12 BA0, BA1 DQ0 to DQ63 CB0 to CB7 /CS0 to /CS3 /RAS /CAS /WE DQMB0 to DQMB7 CLK0 to CLK3 CKE0 REGE* SDA SCL SA0 to SA2 VDD VSS NC 1 Function Address input  Row address A0 to A12  Column address A0 to A9, A11, A12 Bank select address Data input/output Check bit (Data input/output) Chip select input Row enable (/RAS) input Column enable (/CAS) input Write enable input Byte data mask Clock input Clock enable input Register/Buffer enable Data input/output for serial PD Clock input for serial PD Serial address input Primary positive power supply Ground No connection Note: 1. REGE ≥ VIH: Register mode. REGE ≤ VIL: Buffer mode. Data Sheet E0105E50 (Ver. 5.0) 3 EBS21RC2ACNA Serial PD Matrix* Byte No. 0 1 2 3 4 5 6 7 8 9 1 Function described Number of bytes used by module manufacturer Total SPD memory size Memory type Number of row addresses bits Number of column addresses bits Number of banks Module data width Module data width (continued) Module interface signal levels SDRAM cycle time (highest /CAS latency) 7.5ns SDRAM access from Clock (highest /CAS latency) 5.4ns Module configuration type Refresh rate/type SDRAM width Error checking SDRAM width SDRAM device attributes: minimum clock delay for back-toback random column addresses SDRAM device attributes: Burst lengths supported SDRAM device attributes: number of banks on SDRAM device SDRAM device attributes: /CAS latency SDRAM device attributes: /CS latency SD.


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