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EBD21RD4ABNA Dataheets PDF



Part Number EBD21RD4ABNA
Manufacturers Elpida Memory
Logo Elpida Memory
Description 2GB Registered DDR SDRAM DIMM
Datasheet EBD21RD4ABNA DatasheetEBD21RD4ABNA Datasheet (PDF)

PRELIMINARY DATA SHEET 2GB Registered DDR SDRAM DIMM EBD21RD4ABNA (256M words × 72 bits, 2 Banks) Description The EBD21RD4ABNA is a 256M words × 72 bits, 2 bank Double Data Rate (DDR) SDRAM Module, mounted 36 pieces of DDR SDRAM sealed in TCP package. Read and write operations are performed at the cross points of the CK and the /CK. This highspeed data transfer is realized by the 2-bit prefetchpipelined architecture. Data strobe (DQS) both for read and write are available for high speed and rel.

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PRELIMINARY DATA SHEET 2GB Registered DDR SDRAM DIMM EBD21RD4ABNA (256M words × 72 bits, 2 Banks) Description The EBD21RD4ABNA is a 256M words × 72 bits, 2 bank Double Data Rate (DDR) SDRAM Module, mounted 36 pieces of DDR SDRAM sealed in TCP package. Read and write operations are performed at the cross points of the CK and the /CK. This highspeed data transfer is realized by the 2-bit prefetchpipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each TCP on the module board. Note: Do not push the cover or drop the modules in order to avoid mechanical defects, which may result in electrical defects. Features • 184-pin socket type dual in line memory module (DIMM)  PCB height: 30.48mm  Lead pitch: 1.27mm • 2.5V power supply • Data rate: 266Mbps/200Mbps (max.) • 2.5 V (SSTL_2 compatible) I/O • Double Data Rate architecture; two data transfers per clock cycle • Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the receiver • Data inputs and outputs are synchronized with DQS • 4 internal banks for concurrent operation (Component) • DQS is edge aligned with data for READs; center aligned with data for WRITEs • Differential clock inputs (CK and /CK) • LL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data referenced to both edges of DQS • Auto precharge option for each burst access • Programmable burst length: 2, 4, 8 • Programmable /CAS latency (CL): 2, 2.5 • Refresh cycles: (8192 refresh cycles /64ms)  7.8µs maximum average periodic refresh interval • 2 variations of refresh  Auto refresh  Self refresh • 1 piece of PLL clock driver, 1 piece of register driver and 1 piece of serial EEPROM (2k bits EEPROM) for Presence Detect (PD) Document No. E0273E20 (Ver. 2.0) Date Published Aug 2002 (K) Japan URL: http://www.elpida.com Elpida Memory, Inc. 2002 EBD21RD4ABNA Ordering Information Part number EBD21RD4ABNA-7A EBD21RD4ABNA-7B EBD21RD4ABNA-10 Data rate Mbps (max.) 266 266 200 Component JEDEC speed bin*1 (CL-tRCD-tRP) DDR266A (2-3-3) DDR266B (2.5-3-3) DDR200 (2-2-2) Package 184-pin DIMM Contact pad Gold Mounted devices 512M bits DDR SDRAM TCP*2 Notes: 1. Module /CAS latency = component CL + 1 2. Please refer to 512Mb DDR TSOP product datasheet (E0237E) for electrical characteristics. Pin Configurations Front side 1 pin 52 pin 53 pin 92 pin 93 pin Back side 144 pin 145 pin 184 pin Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin name VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC /RESET VSS DQ8 DQ9 DQS1 VDDQ NC NC VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 Pin No. 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 6.


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