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FQI3P50

Fairchild Semiconductor

500V P-Channel MOSFET

FQB3P50 / FQI3P50 August 2000 QFET FQB3P50 / FQI3P50 500V P-Channel MOSFET General Description These P-Channel enhance...


Fairchild Semiconductor

FQI3P50

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Description
FQB3P50 / FQI3P50 August 2000 QFET FQB3P50 / FQI3P50 500V P-Channel MOSFET General Description These P-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for electronic lamp ballast based on complimentary half bridge. TM Features -2.7A, -500V, RDS(on) = 4.9Ω @VGS = -10 V Low gate charge ( typical 18 nC) Low Crss ( typical 9.5 pF) Fast switching 100% avalanche tested Improved dv/dt capability D S ! ● ● G! G S ▶ ▲ ● D2-PAK FQB Series G D S I2-PAK FQI Series ! D Absolute Maximum Ratings Symbol VDSS ID IDM VGSS EAS IAR EAR dv/dt PD TC = 25°C unless otherwise noted Parameter Drain-Source Voltage - Continuous (TC = 25°C) Drain Current - Continuous (TC = 100°C) Drain Current - Pulsed (Note 1) FQB3P50 / FQI3P50 -500 -2.7 -1.71 -10.8 ± 30 (Note 2) (Note 1) (Note 1) (Note 3) Units V A A A V mJ A mJ V/ns W W W/°C °C °C Gate-Source Voltage Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Power Dissipation (TA = 25°C) * 250 -2.7 8.5 -4.5 3.13 85 0.68 -55 to +150 300 TJ, TSTG TL Power Dissipation (TC = 25°C) - Derate above 25°C Operating and Storage Temperature Range Maximum lead temperature for solde...




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