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FPD85310 Dataheets PDF



Part Number FPD85310
Manufacturers National Semiconductor
Logo National Semiconductor
Description Panel Timing Controller
Datasheet FPD85310 DatasheetFPD85310 Datasheet (PDF)

FPD85310 Panel Timing Controller September 1999 FPD85310 Panel Timing Controller General Description The FPD85310 Panel Timing Controller is an integrated FPD-Link based TFT-LCD timing controller. It resides on the flat panel display and provides the interface signal routing and timing control between graphics or video controllers and a TFT-LCD system. FPD-Link is a low power, low electromagnetic interference interface used between this controller and the host system. The FPD85310 chip links t.

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FPD85310 Panel Timing Controller September 1999 FPD85310 Panel Timing Controller General Description The FPD85310 Panel Timing Controller is an integrated FPD-Link based TFT-LCD timing controller. It resides on the flat panel display and provides the interface signal routing and timing control between graphics or video controllers and a TFT-LCD system. FPD-Link is a low power, low electromagnetic interference interface used between this controller and the host system. The FPD85310 chip links the panel’s system interface to the display via a ten wire LVDS data bus. That data is then routed to the source and gate display drivers. XGA and SVGA resolutions are supported. The FPD85310 is programmable via an optional external serial EEPROM. Reserved space in the EEPROM is available for display identification information. The system can access the EEPROM to read the display identification data or program initialization values used by the FPD85310. Features n FPD-Link System Interface utilizes Low Voltage Differential Signaling (LVDS). n System programmable via EEPROM n Suitable for notebook and monitor applications n 8-bit or 6-bit system interface n XGA or SVGA capable n Supports single or dual port column drivers n Programmable outputs provide customized control for standard or in-house column drivers and row drivers n Fail-safe operation prevents panel damage with system clock failure n Programmable skew rate controlled outputs on CD interface for reduced EMI n Polarity pin reduces CD data bus switching n CMOS circuitry operates from a 3.3V supply System Diagram DS101086-1 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS101086 www.national.com Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VDD) DC Input Voltage (VIN) DC Output Voltage (VOUT) Storage Temperature Range (TSTG) Lead Temperature (TL) (Soldering 10 sec.) −0.5V to VDD −0.5V to VDD 4.1V +0.5V +0.5V ESD Rating: (CZAP = 120 pF, RZAP = 1500Ω) MM = 200V, HBM = 2000V Operating Conditions Supply Voltage (VDD) Operating Temp. Range (TA) Min 3.0 0 Max 3.6 70 Units V ˚C −65˚C to +150˚C 260˚C Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. DC Electrical Characteristics Symbol VOH VOL VIH VIL IIN IOZ IDD VTHH VTHL Parameter Minimum High Level Output Voltage Maximum Low Level Output Voltage Minimum High Level Input Voltage Maximum Low Level Input Voltage Input Current Maximum TRI-STATE Output Leakage Current Average Supply Current Differential Input High Threshold Differential Input Low Threshold TA = 0˚C to 70˚C, VDD = 3.3V ± 0.3V.


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