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FMS3818 Dataheets PDF



Part Number FMS3818
Manufacturers Fairchild Semiconductor
Logo Fairchild Semiconductor
Description Triple Video D/A Converter
Datasheet FMS3818 DatasheetFMS3818 Datasheet (PDF)

www.fairchildsemi.com FMS3818 Triple Video D/A Converter 3 x 8 bit, 180 Ms/s Features • • • • • ±2.5% gain matching ±0.5 LSB linearity error Internal bandgap voltage reference Low glitch energy Single 3.3 Volt power supply Description The FMS3818 is a low-cost triple D/A converter, tailored to fit graphics and video applications where speed is critical. CMOS-level inputs are converted to analog current outputs that can drive 25–37.5Ω loads corresponding to doublyterminated 50–75Ω loads. A sync .

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www.fairchildsemi.com FMS3818 Triple Video D/A Converter 3 x 8 bit, 180 Ms/s Features • • • • • ±2.5% gain matching ±0.5 LSB linearity error Internal bandgap voltage reference Low glitch energy Single 3.3 Volt power supply Description The FMS3818 is a low-cost triple D/A converter, tailored to fit graphics and video applications where speed is critical. CMOS-level inputs are converted to analog current outputs that can drive 25–37.5Ω loads corresponding to doublyterminated 50–75Ω loads. A sync current following SYNC input timing is added to the IOG output. BLANK will override RGB inputs, setting IOG, IOB and IOR currents to zero when BLANK = L. Although appropriate for many applications the internal 1.25V reference voltage can be overridden by the VREF input. Few external components are required, just the current reference resistor, current output load resistors, bypass capacitors and decoupling capacitors. Package is a 48-lead LQFP. Fabrication technology is CMOS. Performance is guaranteed from 0 to 70°C. Applications • PC Graphics • Video signal conversion – RGB – YCBCR – Composite, Y, C Block Diagram SYNC BLANK SYNC IOS G7-0 8 8 bit D/A Converter IOG B7-0 8 8 bit D/A Converter IOB R7-0 CLK 8 8 bit D/A Converter IOR COMP RREF VREF +1.25V Ref REV. 1.2.2 11/11/01 FMS3818 PRODUCT SPECIFICATION Functional Description Within the FMS3818 are three identical 8-bit D/A converters, each with a current source output. External loads are required to convert these currents to voltage outputs. Data inputs RGB7-0 are overridden by the BLANK input. SYNC = H activates sync current from IOS for sync-ongreen video signals. VDDA IOS SYNC G7-0 VDDA BLANK gates the D/A inputs. If BLANK = H, the D/A inputs control the output currents to be added to the output blanking level. If BLANK = L, data inputs and the pedestal are disabled. D/A Outputs Each D/A output is a current source from the VDDA supply. Expressed in current units, the GBR transformation from data to current is as follows: G = G7-0 & BLANK + SYNC * 112 B = B7-0 & BLANK R = R7-0 & BLANK Typical LSB current step is 73.2 µA. VDDA B7-0 To obtain a voltage output, a resistor must be connected to ground. Output voltage depends upon this external resistor, the reference voltage, and the value of the gain-setting resistor connected between RREF and GND. To implement a doubly-terminated 75Ω transmission line, a shunt 75Ω resistor should be placed adjacent to the analog output pin. With a terminated 75Ω line connected to the analog output, the load on the FMS3818 current source is 37.5Ω. The FMS3818 may also be operated with a single 75 Ohm terminating resistor. To lower the output voltage swing to the desired range, the nominal value of the RREF resistor should be doubled. VDDA R7-0 Figure 1. FMS3818 Current Source Structure Voltage Reference Full scale current is a multiple of the current ISET through an external resistor, RSET connected between the RREF pin and GND. Voltage across RSET is the reference voltage, VREF, which can be derived from either the 1.25 volt internal bandgap reference or an external voltage reference connected to VREF. To minimize noise, a 0.1µF capacitor should be connected between VREF and ground. ISET is mirrored to each of the GBR output current sources. To minimize noise, a 0.1µF capacitor should be connected between the COMP pin and the analog supply voltage VDDA. Digital Inputs Incoming GBR data is registered on the rising edge of the clock input, CLK. Analog outputs follow the rising edge of CLK after a delay, tDO. SYNC and BLANK SYNC and BLANK inputs control the output level (Figure 1 and Table 1) of the D/A converters during CRT retrace intervals. BLANK forces the D/A outputs to the blanking level while SYNC = L turns off a current source, IOS that is connected to the green D/A converter. SYNC = H adds a 112/256 fraction of full-scale current to the green output. SYNC = L extinguishes the sync current during the sync tip. Power and Ground Required power is a single +3.3 Volt supply. To minimize power supply induced noise, analog +3.3V should be connected to VDDD and VDDA pins with 0.1 and 0.01 µF decoupling capacitors placed adjacent to each VDD pin or pin pair. High slew-rate digital data makes capacitive coupling to the outputs of any D/A converter a potential problem. Since the digital signals contain high-frequency components of the CLK signal, as well as the video output signal, the resulting data feedthrough often looks like harmonic distortion or reduced signal-to-noise performance. All ground pins should be connected to a common solid ground plane for best performance. REV. 1.2.2 11/11/01 data: 700 mV max. sync: 307 mV Figure 2. Nominal Output Levels 2 PRODUCT SPECIFICATION FMS3818 Table 1. Output Voltage Coding VREF = 1.25 V, RREF = 348 Ω, RL = 37.5 Ω RGB7-0 (MSB…LSB) 1111 1111 1111 1111 1111 1110 1111 1101 • • 1000 0000 0111 1111 0111 1111 • • 0000 0010 0000 0001 0000 0000 0000 0000 XXXX XXXX XX.


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