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M25P10-A Dataheets PDF



Part Number M25P10-A
Manufacturers STMicroelectronics
Logo STMicroelectronics
Description 1 Mbit/ Low Voltage/ Serial Flash Memory With 25 MHz SPI Bus Interface
Datasheet M25P10-A DatasheetM25P10-A Datasheet (PDF)

M25P10-A 1 Mbit, Low Voltage, Serial Flash Memory With 25 MHz SPI Bus Interface FEATURES SUMMARY s 1 Mbit of Flash Memory s Figure 1. Packages Page Program (up to 256 Bytes) in 1.5ms (typical) Sector Erase (256 Kbit) in 2 s (typical) Bulk Erase (1 Mbit) in 3 s (typical) 2.7 V to 3.6 V Single Supply Voltage SPI Bus Compatible Serial Interface 25 MHz Clock Rate (maximum) Deep Power-down Mode 1 µA (typical) Electronic Signature (10h) More than 100,000 Erase/Program Cycles per Sector More than 20 .

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M25P10-A 1 Mbit, Low Voltage, Serial Flash Memory With 25 MHz SPI Bus Interface FEATURES SUMMARY s 1 Mbit of Flash Memory s Figure 1. Packages Page Program (up to 256 Bytes) in 1.5ms (typical) Sector Erase (256 Kbit) in 2 s (typical) Bulk Erase (1 Mbit) in 3 s (typical) 2.7 V to 3.6 V Single Supply Voltage SPI Bus Compatible Serial Interface 25 MHz Clock Rate (maximum) Deep Power-down Mode 1 µA (typical) Electronic Signature (10h) More than 100,000 Erase/Program Cycles per Sector More than 20 Year Data Retention s s s s s s s s 8 1 SO8 (MN) 150 mil width s VFQFPN8 (MP) (MLP8) ENHANCED VERSION OF THE M25P10 This device is an enhanced version of the M25P10. The enhanced features include: larger page size, shorter programming time, higher clock frequency. February 2003 1/34 M25P10-A SUMMARY DESCRIPTION The M25P10-A is a 1 Mbit (128K x 8) Serial Flash Memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as 4 sectors, each containing 128 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 512 pages, or 131,072 bytes. The whole memory can be erased using the Bulk Erase instruction, or a sector at a time, using the Sector Erase instruction. Figure 2. Logic Diagram VCC Figure 3. SO and VFQFPN Connections M25P10-A S Q W VSS 1 2 3 4 8 7 6 5 AI05761B VCC HOLD C D D C S W HOLD M25P10-A Q Note: 1. See page 30 (onwards) for package dimensions, and how to identify pin-1. VSS AI05760 Table 1. Signal Names C D Q Serial Clock Serial Data Input Serial Data Output Chip Select Write Protect Hold Supply Voltage Ground S W HOLD VCC VSS 2/34 M25P10-A SIGNAL DESCRIPTION Serial Data Output (Q). This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). Serial Data Input (D). This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C). Serial Clock (C). This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C). Chip Select (S). When this input signal is High, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress, the device will be in the Standby mode (this is not the Deep Power-down mode). Driving Chip Select (S) Low enables the device, placing it in the active power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction. Hold (HOLD). The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don’t Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven Low. Write Protect (W). The main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). 3/34 M25P10-A SPI MODES These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: – CPOL=0, CPHA=0 – CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 5, is the clock polarity when the bus master is in Stand-by mode and not transferring data: – C remains at 0 for (CPOL=0, CPHA=0) – C remains at 1 for (CPOL=1, CPHA=1) Figure 4. Bus Master and Memory Devices on the SPI Bus SDO SPI Interface with (CPOL, CPHA) = (0, 0) or (1, 1) SDI SCK C Q D Bus Master (ST6, ST7, ST9, ST10, Others) SPI Memory Device CS3 CS2 CS1 S W HOLD S W HOLD S W HOLD SPI Memory Device SPI Memory Device C Q D C Q D AI03746D Note: 1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate. Figure 5. SPI Modes Supported CPOL CPHA C 0 0 1 1 C D MSB Q MSB AI01438B 4/34 M25P10-A OPERATING FEATURES Page Programming To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program cycle (of duration tPP). To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecuti.


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