AV9107C-13CS08

Integrated Circuit Systems, Inc. AV9107C-13 CPU Frequency Generator The AV9107C-13 offers a tiny footprint solution for generating two simultaneous clocks. The AV9107C-13 uses a 20 MHz crystal to generate two PLL synthesis outputs of 20 and 40 MHz. The Output enable pin will tristate the 40 MHz output when low (maintaining the 20 MHz output runing in both logic levels). The power pin takes the device to a low current condition, shutting off the PLL and forcing both outputs low, when the PD# pin is low. There is a built-in pull-up on both the OE and PD# inputs. The device has advanced features which include on-chip loop filters, tristate outputs, and power-down capability. A minimum of external components - two decoupling capacitors and an optional ferrite bead - are all that are required for jitterfree operation. General Description • • • • • • • Features Patented on-chip Phase-Locked Loop with VCO for clock generation Provides two synthesized clocks Generates 20 and 40 MHz output frequencies. On-chip loop filter Low power CMOS technology Single +3.3 or +5 volt power supply 8-pin SOIC package Pin Configuration Block Diagram Note: Crystal is 20 MHz AV 9107-13 RevB052197 AV9107C-13 Functionality OE 0 1 (at 14.318) MHz reference frequency input) CLK1 20 MHz 20 MHz CLK2 Tristate 40 MHz Pin Descriptions PIN NUMBER 1 2 3 4 5 6 7 8 PIN NAME OE GND X1/CLK0 X2 PD# CLK1 VDD CLK2 TYPE Input PWR Input Input PWR Output DESCRIPTION Output Enable - Tristates the 40 MHz output ...