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INTEGRATED CIRCUITS
74ALVT16374 2.5V/3.3V 16-bit edge-triggered D-type flip-flop (3-State)
Product specification Supersedes data of 1998 Feb 13 IC23 Data Handbook 1999 Oct 18
Philips Semiconductors
Philips Semiconductors
Product specification
2.5V/3.3V 16-bit edge-triggered D-type flip-flop (3-State)
74ALVT16374
FEATURES
• 16-bit edge-triggered flip-flop • 5V I/O compatibile • 3-State buffers • Output capability: +64mA/-32mA • TTL input and output switching levels • Input and output interface capability to systems at 5V supply • Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
DESCRIPTION
The 74ALVT16374 is a high-performance BiCMOS product designed for VCC operation at 2.5V or 3.3V with I/O compatibility up to 5V. This device is a 16-bit edge-triggered D-type flip-flop featuring non-inverting 3-State outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CP), the Q outputs of the flip-flop take on the logic levels set up at the D inputs.
• Live insertion/extraction permitted • Power-up reset • Power-up 3-State • No bus current loading when output is tied to 5V bus • Latch-up protection exceeds 500mA per JEDEC Std 17 • ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
QUICK REFERENCE DATA
SYMBOL tPLH tPHL CIN COut ICCZ PARAMETER Propagation delay nCP to nQx Input capacitance DIR, OE Output capacitance Total supply current CL = 50pF VI = 0V or VCC Outputs disabled; VO = 0V or VCC Outputs disabled CONDITIONS Tamb = 25°C TYPICAL UNIT 2.5V 2.6 2.8 3 9 40 3.3V 2.1 2.3 3 9 40 ns pF pF µA
ORDERING INFORMATION
PACKAGES 48-Pin Plastic SSOP Type III 48-Pin Plastic TSSOP Type II TEMPERATURE RANGE –40°C to +85°C –40°C to +85°C OUTSIDE NORTH AMERICA 74ALVT16374 DL 74ALVT16374 DGG NORTH AMERICA AV16374 DL AV16374 DGG DWG NUMBER SOT370-1 SOT362-1
1999 Oct 18
2
853-1844 22537
Philips Semiconductors
Product specification
2.5V/3.3V 16-bit edge-triggered D-type flip-flop (3-State)
74ALVT16374
LOGIC SYMBOL
47 46 44 43 41 40 38 37
PIN CONFIGURATION
1OE 1Q0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1CP 1D0 1D1 GND 1D2 1D3 VCC 1D4 1D5 GND 1D6 1D7 2D0 2D1 GND 2D2 2D3 VCC 2D4 2D5 GND 2D6 2D7 2CP
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 48 1 1CP 1OE 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7
!Q1 GND 1Q2 1Q3 VCC
2 36
3 35
5 33
6 32
8 30
9 29
11 27
12 26
1Q4 1Q5 GND 1Q6
2D0 2D21 2D2 2D3 2D4 2D5 2D6 2D7 25 24 2CP 2OE 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7
1Q7 2Q0 2Q1 GND 2Q2
13
14
16
17
19
20
22
23
2Q3 VCC
SW00018
2Q4 2Q5 GND 2Q6
LOGIC SYMBOL (IEEE/IEC)
1OE 1CP 2OE 2CP 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 1 48 24 25 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 2D 2∇ 1EN C1 2EN C2 1D 1∇ 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8
2Q.