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ATMEGA103L Dataheets PDF



Part Number ATMEGA103L
Manufacturers ATMEL Corporation
Logo ATMEL Corporation
Description 8-Bit Microcontroller
Datasheet ATMEGA103L DatasheetATMEGA103L Datasheet (PDF)

Features • Utilizes the AVR® RISC Architecture • AVR – High-performance and Low-power RISC Architecture – 121 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers + Peripheral Control Registers – Up to 6 MIPS Throughput at 6 MHz • Data and Nonvolatile Program Memory – 128K Bytes of In-System Programmable Flash Endurance: 1,000 Write/Erase Cycles – 4K Bytes Internal SRAM – 4K Bytes of In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycl.

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Features • Utilizes the AVR® RISC Architecture • AVR – High-performance and Low-power RISC Architecture – 121 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers + Peripheral Control Registers – Up to 6 MIPS Throughput at 6 MHz • Data and Nonvolatile Program Memory – 128K Bytes of In-System Programmable Flash Endurance: 1,000 Write/Erase Cycles – 4K Bytes Internal SRAM – 4K Bytes of In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles – Programming Lock for Flash Program and EEPROM Data Security – SPI Interface for In-System Programming • Peripheral Features – On-chip Analog Comparator – Programmable Watchdog Timer with On-chip Oscillator – Programmable Serial UART – Master/Slave SPI Serial Interface – Real-time Counter (RTC) with Separate Oscillator – Two 8-bit Timer/Counters with Separate Prescaler and PWM – Expanded 16-bit Timer/Counter System with Separate Prescaler, Compare, Capture Modes and Dual 8-, 9-, or 10-bit PWM – Programmable Watchdog Timer with On-chip Oscillator – 8-channel, 10-bit ADC • Special Microcontroller Features – Low-power Idle, Power-save and Power-down Modes – Software Selectable Clock Frequency – External and Internal Interrupt Sources • Specifications – Low-power, High-speed CMOS Process Technology – Fully Static Operation • Power Consumption at 4 MHz, 3V, 25°C – Active: 5.5 mA – Idle Mode: 1.6 mA – Power-down Mode: < 1 µA • I/O and Packages – 32 Programmable I/O Lines, 8 Output Lines, 8 Input Lines – 64-lead TQFP • Operating Voltages – 2.7 - 3.6V for ATmega103L – 4.0 - 5.5V for ATmega103 • Speed Grades – 0 - 4 MHz for ATmega103L – 0 - 6 MHz for ATmega103 8-bit Microcontroller with 128K Bytes In-System Programmable Flash ATmega103 ATmega103L Note: Not recommended in new designs. Rev. 0945I–AVR–02/07 1 Pin Configuration TQFP PA3 (AD3) PA4 (AD4) PA5 (AD5) PA6 (AD6) PA7 (AD7) ALE PC7 (A15) PC6 (A14) PC5 (A13) PC4 (A12) PC3 (A11) PC2 (A10) PC1 (A9) PC0 (A8) RD WR 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 (AD2) PA2 49 (AD1) PA1 50 (AD0) PA0 51 VCC 52 GND 53 (ADC7) PF7 54 (ADC6) PF6 55 (ADC5) PF5 56 (ADC4) PF4 57 (ADC3) PF3 58 (ADC2) PF2 59 (ADC1) PF1 60 (ADC0) PF0 61 AREF 62 AGND 63 AVCC 64 INDEX CORNER 32 PD7 (T2) 31 PD6 (T1) 30 PD5 29 PD4 (IC1) 28 PD3 (INT3) 27 PD2 (INT2) 26 PD1 (INT1) 25 PD0 (INT0) 24 XTAL1 23 XTAL2 22 GND 21 VCC 20 RESET 19 TOSC1 18 TOSC2 17 PB7 (OC2/PWM2) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PEN (PDI/RXD) PE0 (PDO/TXD) PE1 (AC+) PE2 (AC-) PE3 (INT4) PE4 (INT5) PE5 (INT6) PE6 (INT7) PE7 (SS) PB0 (SCK) PB1 (MOSI) PB2 (MISO) PB3 (OC0/PWM0) PB4 (OC1A/PWM1A) PB5 (OC1B/PWM1B) PB6 2 ATmega103(L) 0945I–AVR–02/07 Description ATmega103(L) The ATmega103(L) is a low-power, CMOS, 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega103(L) achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. The AVR core is based on an enhanced RISC architecture that combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega103(L) provides the following features: 128K bytes of In-System Programmable Flash, 4K bytes EEPROM, 4K bytes SRAM, 32 general purpose I/O lines, 8 input lines, 8 output lines, 32 general purpose working registers, Real Time Counter (RTC), 4 flexible Timer/Counters with compare modes and PWM, UART, programmable Watchdog Timer with internal Oscillator, an SPI serial port and 3 software-selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next Interrupt or Hardware Reset. In Power-save mode, the Timer Oscillator continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On-chip ISP Flash allows the Program memory to be reprogrammed In-System through a serial interface or by a conventional nonvolatile memory programmer. By combining an 8-bit RISC CPU with a large array of ISP Flash on a monolithic chip, the Atmel ATmega103(L) is a powerful microcontroller that provides a highly flexible and cost-effective solution to many embedded control applications. The ATmega103(L) AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, InCircuit Emulators and evaluat.


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