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DS90CR283 Dataheets PDF



Part Number DS90CR283
Manufacturers National Semiconductor
Logo National Semiconductor
Description 28-Bit Channel Link
Datasheet DS90CR283 DatasheetDS90CR283 Datasheet (PDF)

DS90CR283/DS90CR284 28-Bit Channel Link-66 MHz July 1997 DS90CR283/DS90CR284 28-Bit Channel Link-66 MHz General Description The DS90CR283 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CR284 receiver converts the LVDS data streams back i.

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DS90CR283/DS90CR284 28-Bit Channel Link-66 MHz July 1997 DS90CR283/DS90CR284 28-Bit Channel Link-66 MHz General Description The DS90CR283 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CR284 receiver converts the LVDS data streams back into 28 bits of CMOS/TTL data. At a transmit clock frequency of 66 MHz, 28 bits of TTL data are transmitted at a rate of 462 Mbps per LVDS data channel. Using a 66 MHz clock, the data throughput is 1.848 Gbit/s (231 Mbytes/s). The multiplexing of the data lines provides a substantial cable reduction. Long distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability). Thus, for a 28-bit wide data bus and one clock, up to 58 conductors are required. With the Channel Link chipset as few as 11 conductors (4 data pairs, 1 clock pair and a minimum of one ground) are needed. This provides a 80% reduction in required cable width, which provides a system cost savings, reduces connector physical size and cost, and reduces shielding requirements due to the cables’ smaller form factor. The 28 CMOS/TTL inputs can support a variety of signal combinations. For example, 7 4-bit nibbles or 3 9-bit (byte + parity) and 1 control. Features n n n n n n n n n n n 66 MHz clock support Up to 231 Mbytes/s bandwidth Low power CMOS design ( < 610 mW) Power Down mode ( < 0.5 mW total) Up to 1.848 Gbit/s data throughput Narrow bus reduces cable size and cost 290 mV swing LVDS devices for low EMI PLL requires no external components Low profile 56-lead TSSOP package Rising edge data strobe Compatible with TIA/EIA-644 LVDS Standard Block Diagrams DS90CR283 DS90CR284 DS012889-27 DS012889-1 Order Number DS90CR283MTD See NS Package Number MTD56 Order Number DS90CR284MTD See NS Package Number MTD56 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1998 National Semiconductor Corporation DS012889 www.national.com Pin Diagrams DS90CR283 DS90CR284 DS012889-21 DS012889-22 Typical Application DS012889-23 www.national.com 2 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) −0.3V to +6V CMOS/TTL Input Voltage −0.3V to (VCC + 0.3V) CMOS/TTL Ouput Voltage −0.3V to (VCC + 0.3V) LVDS Receiver Input Voltage −0.3V to (V CC + 0.3V) LVDS Driver Output Voltage −0.3V to (VCC + 0.3V) LVDS Output Short Circuit Duration Continuous Junction Temperature +150˚C Storage Temperature Range −65˚C to +150˚C Lead Temperature (Soldering, 4 sec.) +260˚C Maximum Package Power Dissipation @ +25˚C MTD56(TSSOP) Package: DS90CR283 1.63W DS90CR284 1.61W Package Derating: DS90CR283 12.5 mW/˚C above +25˚C DS90CR284 12.4 mW/˚C above +25˚C This device does not meet 2000V ESD rating (Note 4) Recommended Operating Conditions Supply Voltage (VCC) Operating Free Air Temperature (TA) Receiver Input Range Supply Noise Voltage (VCC) Min 4.75 −10 0 Nom 5.0 +25 Max 5.25 +70 2.4 Units V ˚C V 100 mVP-P Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol VIH VIL VOH VOL VCL IIN IOS VOD ∆VOD VOS ∆VOS Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Clamp Voltage Input Current Output Short Circuit Current Differential Output Voltage Change in VOD between Complementary Output States Offset Voltage Change in Magnitude of VOS between Complementary Output States Output Short Circuit Current Output TRI-STATE ® Current Differential Input High Threshold Differential Input Low Threshold Input Current VIN = +2.4V, VCC = 5.0V VIN = 0V, VCC = 5.0V RL = 100Ω, C (Figures 1, 2) ICCTZ Transmitter Supply Current, Power Down Power Down = Low Driver Outputs in TRI-STATE under Power Down Mode 1 25 µA = 5 pF, f = 32.5 MHz f = 37.5 MHz f = 66 MHz 49 51 70 VOUT = OV, R L = 100Ω Power Down = 0V, VOUT = 0V or VCC VCM = +1.2V −100 −2.9 1.1 1.25 1.375 35 V mV IOH = −0.4 mA IOL = 2 mA ICL = −18 mA VIN = VCC, GND, 2.5V or 0.4V VOUT = 0V RL = 100Ω 250 Conditions Min 2.0 GND 3.8 4.9 0.1 −0.79 0.3 −1.5 Typ Max VCC 0.8 Units V V V V V µA mA mV mV CMOS/TTL DC SPECIFICATIONS ± 5.1 ± 10 −120 LVDS DRIVER DC SPEClFlCATIONS 290 450 35 IOS IOZ VTH VTL IIN −5 mA µA mV mV µA µA mA mA mA ±1 ± 10 +100 LVDS RECEIVER DC SPECIFlCATIONS ± 10 ± 10 63 64 84 TRANSMITTER SUPPLY CURRENT ICCTW Transmitter Supply Current, Worst Case L Worst Case Pattern 3 www.national.com Electrical Characteristics Symbol ICCRW Parameter Receiver Supply Current, Worst Case Receiver Supply Current, Power Down (Continued) Over recommended operati.


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