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FDS8926A Dataheets PDF



Part Number FDS8926A
Manufacturers Fairchild Semiconductor
Logo Fairchild Semiconductor
Description Dual N-Channel MOSFET
Datasheet FDS8926A DatasheetFDS8926A Datasheet (PDF)

February 1998 FDS8926A Dual N-Channel Enhancement Mode Field Effect Transistor General Description SO-8 N-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to provide superior switching performance and minimize on-state resistance. These devices are particularly suited for low voltage applications such as disk drive motor control, battery powered circuits w.

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February 1998 FDS8926A Dual N-Channel Enhancement Mode Field Effect Transistor General Description SO-8 N-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to provide superior switching performance and minimize on-state resistance. These devices are particularly suited for low voltage applications such as disk drive motor control, battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed. Features 5.5 A, 30 V. RDS(ON) = 0.030 Ω @ VGS = 4.5 V RDS(ON) = 0.038 Ω @ VGS = 2.5 V. High density cell design for extremely low RDS(ON). Combines low gate threshold (fully enhanced at 2.5V) with high breakdown voltage of 30 V. High power and current handling capability in a widely used surface mount package. Dual MOSFET in surface mount package. SOT-23 SuperSOTTM-6 SuperSOTTM-8 SO-8 SOT-223 SOIC-16 D2 D1 D1 D2 5 6 G2 7 8 4 3 2 1 S FD 6A 2 89 S2 G1 SO-8 pin 1 S1 Absolute Maximum Ratings Symbol VDSS VGSS ID PD Parameter Drain-Source Voltage Gate-Source Voltage Drain Current - Continuous - Pulsed TA = 25oC unless other wise noted FDS8926A 30 ±8 (Note 1a) Units V V A 5.5 20 2 Power Dissipation for Dual Operation Power Dissipation for Single Operation (Note 1a) (Note 1b) (Note 1c) W 1.6 1 0.9 -55 to 150 °C TJ,TSTG RθJA RθJC Operating and Storage Temperature Range THERMAL CHARACTERISTICS Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case (Note 1a) (Note 1) 78 40 °C/W °C/W FDS8926A Rev.B © 1998 Fairchild Semiconductor Corporation Electrical Characteristics (TA = 25 OC unless otherwise noted ) Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Zero Gate Voltage Drain Current VGS = 0 V, I D = 250 µA ID = 250 µA, Referenced to 25 C VDS = 24 V, VGS = 0 V TJ = 55°C IGSSF IGSSR VGS(th) Gate - Body Leakage, Forward Gate - Body Leakage, Reverse (Note 2) o 30 32 1 10 100 -100 V mV / oC µA µA nA nA ∆BVDSS/∆TJ IDSS VGS = 8 V, VDS = 0 V VGS = -8 V, VDS = 0 V VDS = VGS, ID = 250 µA ID = 250 µA, Referenced to 25oC VGS = 4.5 V, I D = 5.5 A TJ =125°C VGS = 2.5 V, I D = 4.5 A 0.4 0.67 -3 0.025 0.037 0.031 20 20 ON CHARACTERISTICS Gate Threshold Voltage Gate Threshold Voltage Temp. Coefficient Static Drain-Source On-Resistance 1 V mV /oC ∆VGS(th)/∆TJ RDS(ON) 0.03 0.052 0.038 Ω ID(ON) gFS Ciss Coss Crss tD(on) tr tD(off) tf Qg Qgs Qgd IS VSD Notes: On-State Drain Current Forward Transconductance VGS = 4.5 V, VDS = 5 V VDS = 5 V, I D = 5.5 A VDS = 10 V, VGS = 0 V, f = 1.0 MHz A S DYNAMIC CH ARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance (Note 2) 900 410 110 pF pF pF SWITCHING CHARACTERISTICS Turn - On Delay Time Turn - On Rise Time Turn - Off Delay Time Turn - Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge VDS = 6 V, I D = 1 A VGS = 4.5 V , RGEN = 6 Ω 6 19 42 13 12 31 67 24 28 ns VDS = 10 V, I D = 5.5 A, VGS = 4.5 V 19.8 2 6.3 nC DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS Maximum Continuous Drain-Source Diode Forward Current Drain-Source Diode Forward Voltage VGS = 0 V, I S = 1.3 A (Note 2) 1.3 0.68 1.2 A V 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. a. 78OC/W on a 0.5 in2 pad of 2oz copper. b. 125OC/W on a 0.02 in2 pad of 2oz copper. c. 135OC/W on a 0.003 in2 pad of 2oz copper. Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. FDS8926A Rev.B Typical Electrical Characteristics 30 I D , DRAIN-SOURCE CURRENT (A) 25 20 2.0V 15 10 5 0 3.5V DRAIN-SOURCE ON-RESISTANCE VGS = 4.5V 1.8 3.0V 2.5V R DS(ON) , NORMALIZED 1.6 VGS = 2.0V 1.4 2.5V 1.2 3.0V 3.5V 4.5V 1.5V 1 0 0.5 1 1.5 2 2.5 3 0.8 0 5 10 15 20 25 VDS , DRAIN-SOURCE VOLTAGE (V) I D , DRAIN CURRENT (A) Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 1.8 DRAIN-SOURCE ON-RESISTANCE R DS(ON) , NORMALIZED 0.1 R DS(ON) , ON-RESISTANCE (OHM) 1.6 1.4 1.2 1 0.8 0.6 -50 I D = 5.5 A VGS = 4.5 V 0.075 I D = 2.8A 0.05 TA = 125°C 0.025 TA = 25°C 0 1 V 2 GS -25 0 25 50 75 100 125 150 3 4 5 TJ , JUNCTION TEMPERATURE (°C) , GATE TO SOURCE VOLTAGE (V) Figure 3. On-Resistance Variation With Temperature. Figure 4. On-Resistance Variation with Gate-to-Source Voltage. 20 20 V DS =5V I D , DRAIN CURRENT (A) 16 25°C 125°C I S , REVERSE DRAIN CURRENT (A) TA = -55°C V GS = 0V 1 TA= 125°C 0.1 12 25°C -55°C 8 0.01 4 0.001 0 0 0.5 1 1.5 2 2.5 3 0.0001 VGS , GATE TO SOURCE VOLTAGE (V) 0 0.2 0.4 0.6 0.8 1 1.2.


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