Document
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FC106
Fibre Channel Transceiver 1.0625 GBaud
PRELIMINARY DATA
FEATURES
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Serial Link Transceiver
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serializer and deserializer implementing the Fibre Channel FC0 and FC1 layers
Parallel Interface
Receive Byte Clock
REFCLK
10 bits
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Direct support for 1.0625 GBaud Fibre Channel (ANSI X3.230-1994) rates Fibre Channel 10-bit Interface (ANSI TR/X3.18-199X) Direct interfaces to optical tranceivers Plesiochronous mode operation
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8 bit / 10 bit DECODER (optional)
8 bit / 10 bit ENCODER (optional)
transmitter and receiver clock frequencies may differ by up to 100 ppm
DESER IALIZER CLOCK RECOVERY BYTE AND WORD ALIGNEMENT
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Integrated Fibre Channel 8b/10b encode/decode (optional use through JTAG) Byte and word synchronization of incoming serial stream Supports any DC-balanced encoding scheme Internal Loop-Back for Self-Test Random Pattern Auto-Test Optional integrated impedance adaptation to transmission line characteristics (50 or 75 ohms) TTL compatible parallel I/O’s JTAG Test Access Port 0.35 µ CMOS Technology for low cost and low power PQFP package available in two sizes: 14x14 mm (FC106/14) or 10x10 mm (FC106/10)
SERIALI ZER AND CLOCK FREQUENCY MULTIPLICATION
FC 106
1.0625 Gbaud Serial data over copper or optical cables
APPLICATIONS
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Fibre Channel Arbitrated Loop Fibre Channel fabric Transmission schemes encoding bytes as 10-bit characters to form a DC-balanced stream High performance backplane interconnect
1/32 September 98 Revision 1.2
FC106
Table of Contents
1 2 3 General Description - - - - - - - - - - - - - - - - - - - - - - 4 Interface Diagram - - - - - - - - - - - - - - - - - - - - - - - 6 Functional Description - - - - - - - - - - - - - - - - - - - - 7 3.1 Block diagram - - - - - - - - - - - - - - - - - - - - - - - 8 3.2 Input latches - - - - - - - - - - - - - - - - - - - - - - - - 8 3.3 8bit/10bit Encoder/Decoder - - - - - - - - - - - - - - - - - 9 3.4 DLL clock generator - - - - - - - - - - - - - - - - - - - - 9 3.5 Serializer functional description and reference clock - - - - - 9 3.6 Serializer latches and XOR-tree - - - - - - - - - - - - - - 10 3.7 Serial input multiplexer - - - - - - - - - - - - - - - - - - 10 3.8 Deserializer functional description - - - - - - - - - - - - - 10 3.9 Bit alignment - - - - - - - - - - - - - - - - - - - - - - - 11 3.10 Byte and word alignment - - - - - - - - - - - - - - - - 12
3.11 Clock recovery - - - - - - - - - - - - - - - - - - - - - 12 3.12 Serial input-output buffer - - - - - - - - - - - - - - - - 13
3.13 I/O impedance control - - - - - - - - - - - - - - - - - - 14 3.14 Self-test - - - - - - - - - - - - - - - - - - - - - - - - - 15 4 5 Serial I/O Electrical Model - - - - - - - - - - - - - - - - - 16
Electrical Specifications - - - - - - - - - - - - - - - - - - 17 5.1 Absolute maximum ratings - - - - - - - - - - - - - - - - 17 5.2 Operating conditions - - - - - - - - - - - - - - - - - - - 17 5.3 DC characteristics - - - - - - - - - - - - - - - - - - - - 18
2/32 September 98 Revision 1.2
FC106 6 Timing Specifications - - - - - - - - - - - - - - - - - - - - 20 6.1 Transmit interface timing and latency - - - - - - - - - - - 20 6.2 Receive interface timing - - - - - - - - - - - - - - - - - 21 6.2.1 Receive clock timing and latency - - - - - - - - - - - 21 6.2.2 Receive interface timing - - - - - - - - - - - - - - - 23 6.3 Serial Input/output AC characteristics - - - - - - - - - - - 24 7 FC106 Pin Description - - - - - - - - - - - - - - - - - - - 25 7.1 Pin summary - - - - - - - - - - - - - - - - - - - - - - - 25 7.2 Pin functions - - - - - - - - - - - - - - - - - - - - - - - 26 8 Package Specifications - - - - - - - - - - - - - - - - - - - 29 8.1 FC106 64-pin PQFP pinout - - - - - - - - - - - - - - - - 29 8.2 FC106 64-pin Quad Flat-pack package dimensions - - - - 30 8.2.1 FC106/14: 14x14 mm package dimensions - - - - - - 30 8.2.2 FC106/10: 10x10 mm package dimensions - - - - - - 31
3/32 September 98 Revision 1.2
FC106
1
General Description
The FC106 Fibre Channel transceiver chip implements the lower layer protocols of the ANSI X3.230-1994 Fibre Channel standard. The Fibre Channel standard specifies the mapping of various upper layer protocols (ULP) such as SCSI, IP and HiPPI to a common lower layer protocol, together with appropriate electrical and optical high performance specifications. Fibre Channel provides a channel over which concurrent communication of a variety of ULP’s may exist on a single interconnect between workstations, mainframes and supercomputers, and provides a connection to mass storage devices and other peripherals. The FC106 implements the Fibre Channel electrical transceiver physical layer specification for 1.0625 Gbit/s. At this frequency, the Fibre Channel delivers 100 MByte/s of data bandwidth over a twin coaxial or twin optical fibre cable. This bandwidth equals or exceeds most bus bandwidths. The FC106 chip performs the high speed serialization and deserialization f.