M2020

Integrated Circuit Systems, Inc. Product Data Sheet M2020/21 VCSO BASED CLOCK PLL GENERAL DESCRIPTION The M2020/21 is a VCSO (Voltage Controlled SAW Oscillator) based clock jitter attenuator PLL designed for clock jitter attenuation and frequency translation. The device is ideal for generating the transmit reference clock for optical network systems supporting 2.5-10 GB data rates. It can serve to jitter attenuate a stratum reference clock or a recovered clock in loop timing mode. The M2020/21 module includes a proprietary SAW (surface acoustic wave) delay line as part of the VCSO. This results in a high frequency, high-Q, low phase noise oscillator that assures low intrinsic output jitter. PIN ASSIGNMENT (9 x 9 mm SMT) FIN_SEL1 GND P_SEL2 DIF_REF0 nDIF_REF0 REF_SEL DIF_REF1 nDIF_REF1 VCC FIN_SEL0 MR_SEL0 MR_SEL1 LOL NBW VCC DNC DNC DNC 27 26 25 24 23 22 21 20 19 28 29 30 31 32 33 34 35 36 M2020 M2021 (Top View) 18 17 16 15 14 13 12 11 10 P_SEL0 P_SEL1 nFOUT0 FOUT0 GND nFOUT1 FOUT1 VCC GND FEATURES ◆ Integrated SAW (surface acoustic wave) delay line; low phase jitter of < 0.5ps rms, typical (12kHz to 20MHz or 50kHz to 80MHz) ◆ Output frequencies of 15 to 700 MHz * ◆ LVPECL clock output (CML and LVDS options available) ◆ Reference clock inputs support differential LVDS, LVPECL, as well as single-ended LVCMOS, LVTTL ◆ Loss of Lock (LOL) output pin ◆ Narrow Bandwidth control input (NBW pin) ◆ Hitless Switching (HS) options with or without Phase Build-out (PBO) available...