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M-8888 Dataheets PDF



Part Number M-8888
Manufacturers Clare Inc.
Logo Clare  Inc.
Description DTMF Transceiver
Datasheet M-8888 DatasheetM-8888 Datasheet (PDF)

M-8888 DTMF Transceiver Features CMOS technology for low power con· Advanced sumption and increased noise immunity DTMF transmitter/receiver in a single · Complete chip Standard 8051, 8086/8 microprocessor port · Central office quality and performance · Adjustable guard time · Automatic tone burst mode · Call progress mode · Single +5 Volt power supply · 20-pin DIP and SOIC packages · 2 MHz microprocessor port operation · · Inexpensive 3.58 MHz crystal Applications Paging systems · Repeater syst.

  M-8888   M-8888


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M-8888 DTMF Transceiver Features CMOS technology for low power con· Advanced sumption and increased noise immunity DTMF transmitter/receiver in a single · Complete chip Standard 8051, 8086/8 microprocessor port · Central office quality and performance · Adjustable guard time · Automatic tone burst mode · Call progress mode · Single +5 Volt power supply · 20-pin DIP and SOIC packages · 2 MHz microprocessor port operation · · Inexpensive 3.58 MHz crystal Applications Paging systems · Repeater systems/mobile radio · Interconnect dialers · PBX systems · Computer systems · Fax machines · Pay telephone · · Credit card verification Description The M-8888 is a complete DTMF Transmitter Receiver that features adjustable guard time, automatic tone burst mode, call progress mode, and a fully compatible 8051, 8086/8 microprocessor interface. The receiver portion is based on the industry standard M-8870 DTMF Receiver, while the transmitter uses a switched-capacitor digital-to-analog converter for lowdistortion, highly accurate DTMF signaling. Tone bursts can be transmitted with precise timing by making use of the automatic tone burst mode. To analyze call progress tones, a call progress filter can be selected by an external microprocessor. Ordering Information Part # Description M-8888-01P M-8888-01SM M-8888-01T 20-pin plastic DIP 20-pin plastic SOIC 20-pin plastic SOIC,Tape and Reel Pin Connections Block Diagram DS-M8888-R1 www.clare.com 1 M-8888 Single-Ended Input Configuration Differential Input Configuration Functional Description M-8888 functions consist of a high-performance DTMF receiver with an internal gain setting amplifier and a DTMF generator that contains a tone burst counter for generating precise tone bursts and pauses. The call progress mode, when selected, allows the detection of call progress tones. A standard 8051, 8086/8 series microprocessor interface allows access to an internal status register, two control registers, and two data registers. Input Configuration The input arrangement consists of a differential input operational amplifier and bias sources (VREF) for biasPin Functions Name IN+ INGS VREF VSS OSC1 OSC2 TONE WR CS RS0 RD IRQ /CP Description Noninverting op-amp input. Inverting op-amp input. Gain select. Gives access to output of front end differential amplifier for connection of feedback resistor. Reference voltage output. Nominally VDD/2 is used to bias inputs at mid-rail. Negative power supply input. DTMF clock/oscillator input. Clock output. A 3.5795 MHz crystal connected between OSC1 and OSC2 completes the internal oscillator circuit. Dual tone multifrequency (DTMF) output. Write input. A low on this pin when CS is low enables data transfer from the microprocessor. TTL compatible. Chip select. TTL input (CS = 0 to select the chip). Register select input. See Internal Register Functions on page 7. TTL compatible. Read input. A low on this pin when CS is low enables data transfer to the microprocessor. TTL compatible.. Interrupt request to microprocessor (open-drain output). Also, when call progress (CP) mode has been selected and interrupt enabled, the IRQ/CP pin will output a rectangular wave signal representative of the input signal applied at the input op-amp. The input signal must be within the bandwidth limits of the call progress filter. See Timing Diagrams on page 11. Microprocessor data bus. TTL compatible. Early steering output. Presents a logic high once the digital algorithm has detected a valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low. Steering input/guard time output (bidirectional). A voltage greater than VTSt detected at St causes the device to register the detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to reset the external steering time-constant; its state is a function of ESt and the voltage on St. Positive power supply input. ing the amplifier inputs at VDD/2. Provisions are made for the connection of a feedback resistor to the op-amp output (GS) for gain adjustment. In a single-ended configuration, the input pins should be connected as shown in the Single-Ended Input Configuration above. Differential Input Configuration above shows the necessary connections for a differential input configuration. Receiver Section The low and high group tones are separated by applying the DTMF signal to the inputs of two sixth-order D0-D3 ESt St/GT VDD 2 www.clare.com Rev. 1 M-8888 switched capacitor bandpass filters with bandwidths that correspond to the low and high group frequencies listed in the Tone Encoding/Decoding below. The low group filter incorporates notches at 350 and 440 Hz, providing excellent dial tone rejection. Each filter output is followed by a single-order switched capacitor filter that smoothes the signals prior to limiting. Limiting is performed by high-gain comparators with hysteresis to pr.


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