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2SK2553S Dataheets PDF



Part Number 2SK2553S
Manufacturers Hitachi Semiconductor
Logo Hitachi Semiconductor
Description Silicon N Channel MOS FET
Datasheet 2SK2553S Datasheet2SK2553S Datasheet (PDF)

2SK2553(L), 2SK2553(S) Silicon N Channel MOS FET High Speed Power Switching ADE-208-357H (Z) 9th. Edition February 1999 Application High speed power switching Features • • • • Low on-resistance R DS(on) = 7 mΩ typ. High speed switching 4 V gate drive device can be driven from 5 V source Outline LDPAK 4 4 1 2 1 D G 2 3 3 S 1. Gate 2. Drain 3. Source 4. Drain 2SK2553(L), 2SK2553(S) Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate to source voltage Drain current Drain.

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2SK2553(L), 2SK2553(S) Silicon N Channel MOS FET High Speed Power Switching ADE-208-357H (Z) 9th. Edition February 1999 Application High speed power switching Features • • • • Low on-resistance R DS(on) = 7 mΩ typ. High speed switching 4 V gate drive device can be driven from 5 V source Outline LDPAK 4 4 1 2 1 D G 2 3 3 S 1. Gate 2. Drain 3. Source 4. Drain 2SK2553(L), 2SK2553(S) Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate to source voltage Drain current Drain peak current Body to drain diode reverse drain current Avalanche current Avalanche energy Channel dissipation Channel temperature Storage temperature Notes 1. PW ≤ 10 µs, duty cycle ≤ 1 % 2. Value at Tc = 25 °C 3. Value at Tch = 25 °C, Rg ≥ 50 Ω Symbol VDSS VGSS ID I D(pulse) I DR I AP Note 3 Note 3 Note 2 Note 1 Ratings 60 ±20 50 200 50 45 174 75 150 –55 to +150 Unit V V A A A A mJ W °C °C EAR Pch Tch Tstg 2 2SK2553(L), 2SK2553(S) Electrical Characteristics (Ta = 25°C) Item Drain to source breakdown voltage Gate to source breakdown voltage Gate to source leak current Symbol V(BR)DSS V(BR)GSS I GSS Min 60 ±20 — — 1.0 — — Forward transfer admittance Input capacitance Output capacitance Reverse transfer capacitance Turn-on delay time Rise time Turn-off delay time Fall time Body to drain diode forward voltage Body to drain diode reverse recovery time Note 1. Pulse Test |yfs| Ciss Coss Crss t d(on) tr t d(off) tf VDF t rr 35 — — — — — — — — — Typ — — — — — 7 10 55 3550 1760 500 35 230 470 360 0.85 135 Max — — ±10 10 2.0 10 16 — — — — — — — — — — Unit V V µA µA V mΩ mΩ S pF pF pF ns ns ns ns V ns I F = 50 A, VGS = 0 I F = 50 A, VGS = 0 diF / dt = 50 A / µs Test Conditions I D = 10 mA, VGS = 0 I G = ±100 µA, VDS = 0 VGS = ±16 V, VDS = 0 VDS = 60 V, VGS = 0 I D = 1 mA, VDS = 10 V I D = 25 A VGS = 10 V Note 1 I D = 25 A VGS = 4 V Note 1 I D = 25 A VDS = 10 V Note 1 VDS = 10 V VGS = 0 f = 1 MHz I D = 25 A VGS = 10 V RL = 1.2 Ω Zero gate voltage drain current I DSS Gate to source cutoff voltage Static drain to source on state resistance VGS(off) RDS(on) See characteristic curves of 2SK2529. 3 2SK2553(L), 2SK2553(S) Maximum Safe Operation Area 10 PW C D O Power vs. Temperature Derating 100 Pch (W) I D (A) 500 200 100 50 20 10 5 2 1 10 = µs 75 0 1 10 m s µs m Channel Dissipation Drain Current s sh ot pe tio ra 50 (1 n Operation in this area is limited by R DS(on) c (T = ) 25 ) °C 25 0 50 100 150 Tc (°C) 200 Case Temperature Ta = 25 °C 0.5 3 30 0.1 0.3 1 10 100 Drain to Source Voltage V DS (V) Normalized Transient Thermal Impedance vs. Pulse Width 3 Normalized Transient Thermal Impedance γ s (t) Tc = 25°C 1 D=1 0.5 0.3 0.2 0.1 0.1 0.05 θ ch – c(t) = γ s (t) • θ ch – c θ ch – c = 1.67 °C/W, Tc = 25 °C PDM PW T 0.03 0.02 1 lse 0.0 t pu o h 1s D= PW T 0.01 10 µ 100 µ 1m 10 m Pulse Width 100 m PW (S) 1 10 4 2SK2553(L), 2SK2553(S) Avalanche Test Circuit Avalanche Waveform 1 2 • L • I AP • 2 VDSS VDSS – V DD V DS Moni.


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