CXL5505P

CXL5505M/P CMOS-CCD 1H Delay Line for PAL Description The CXL5505M/P are CMOS-CCD delay line ICs that provide 1H delay time for PAL signals including the external low-pass filter. Features Single 5V power supply Low power consumption 100mW (Typ.) Built-in peripheral circuits Built-in quadruple PLL circuit Functions 1130-bit CCD register Clock driver Auto-bias circuit Input clamp circuit Sample-and-hold circuit PLL circuit Structure CMOS-CCD CXL5505M 14 pin SOP (Plastic) CXL5505P 14 pin DIP (Plastic) Absolute Maximum Ratings (Ta = 25°C) Supply voltage VDD 6 V Operating temperature Topr –10 to +60 °C Storage temperature Tstg –55 to +150 °C Allowable power dissipation PD CXL5505M 400 mW CXL5505P 800 mW Recommended Operating Condition (Ta = 25°C) Supply voltage VDD 5 ± 5% V Recommended Clock Conditions (Ta = 25°C) Input clock amplitude VCLK 0.3 to 1.0 Vp-p (0.5Vp-p typ.) Clock frequency fCLK 4.433619 MHz Input clock waveform Sine wave Input Signal Amplitude VSIG 575mVp-p (Max.) (at internal clamp condition) Blook Diagram and Pin Configuration (Top View) VCO IN PC OUT CLK 8 PLL Timing circuit Bias circuit (A) Output circuit (S/H 1bit) Clamp circuit Bias circuit (B) 7 VDD 14 13 AB 12 11 10 Auto-bias circuit CCD (1130bit) Clock driver 1 2 3 4 5 VG2 VSS IN OUT VG1 VSS VDD 9 6 VSS Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication...