CXL5002P

CXL5002M/P CMOS-CCD 1/2H Delay Line for NTSC Description The CXL5002M/P are general-purpose CMOS-CCD delay line ICs that provide 1/2H delay time for NTSC. Features Low power consumption 70mW (Typ.) Small size package (8-pin SOP, DIP) Low differential gain DG = 3% (Typ.) Input signal amplitude 180 IRE (= 1.28Vp-p, Max.) Low input clock amplitude operation 150mVp-p (Min.) Built-in peripheral circuits (clock driver, timing generator, autobias, and output circuits) Functions 340-bit CCD register Clock drivers Autobias circuit Sync tip clamp circuit Sample and hold circuit Structure CMOS-CCD Absolute Maximum Ratings (Ta = 25°C) Supply voltage VDD 11 V Supply voltage VCL 6 V Operating temperature Topr –10 to +60 °C Storage temperature Tstg –55 to +150 °C Allowable power dissipation PD CXL5002M 350 mW CXL5002P 480 mW Recommended Operating Conditions Supply voltage VDD 9 ± 5% V VCL 5 ± 5% V Recommended Clock Conditions Input clock amplitude VCK 150mVp-p to 1.0Vp-p (250mVp-p typ.) Clock frequency fCK 10.7MHz Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. CXL5002M 8 pin SOP (Plastic) CXL5002P 8 pin DIP (Plastic) ...