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CXL5001P Dataheets PDF



Part Number CXL5001P
Manufacturers Sony Corporation
Logo Sony Corporation
Description CMOS-CCD 1H Delay Line for NTSC
Datasheet CXL5001P DatasheetCXL5001P Datasheet (PDF)

CXL5001M/P CMOS-CCD 1H Delay Line for NTSC Description The CXL5001M/P are general-purpose CMOS-CCD delay line ICs that provide 1H delay time for NTSC. Features • Low power consumtion 80mW (Typ.) • Small size package (8-pin SOP, DIP) • Low differential gain DG = 3% (Typ.) • Input signal ampiitude 180 IRE (= 1.28Vp-p, Max.) • Low input clock amplitude operation 150mVp-p (Min.) • Built-in peripheral circuits (clock driver, timing generator, autobias, and output circuits) Functions • 680-bit CCD reg.

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CXL5001M/P CMOS-CCD 1H Delay Line for NTSC Description The CXL5001M/P are general-purpose CMOS-CCD delay line ICs that provide 1H delay time for NTSC. Features • Low power consumtion 80mW (Typ.) • Small size package (8-pin SOP, DIP) • Low differential gain DG = 3% (Typ.) • Input signal ampiitude 180 IRE (= 1.28Vp-p, Max.) • Low input clock amplitude operation 150mVp-p (Min.) • Built-in peripheral circuits (clock driver, timing generator, autobias, and output circuits) Functions • 680-bit CCD register • Clock drivers • Autobias circuit • Sync tip clamp circuit • Sample and hold circuit Structure CMOS-CCD Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VDD 11 V • Supply voltage VCL 6 V • Operating temperature Topr –10 to +60 °C • Storage temperature Tstg –55 to +150 °C • Allowable power dissipation PD CXL5001M 350 mW CXL5001P 480 mW Recommended Operating Conditions Supply voltage VDD 9 ± 5% V VCL 5 ± 5% V Recommended Clock Conditions • Input clock amplitude VCLK 150mVp-p to 1.0Vp-p (250mVp-p typ.) • Clock frequency fCLK 10.7MHz Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. CXL5001M 8 pin SOP (Plastic) CXL5001P 8 pin DIP (Plastic) –1– E50799A78-PS CXL5001M/P Blook Diagram AUTO FEED OUT 5 ref. (1 BIT) CLAMP CIRCUIT 680-BIT SHIFT REGISTER φ1 φ2 AMP S/H φ1 AMP φ2 AMP 4 IN 8 7 6 AUTOBIAS CIRCUIT CLOCK DRIVERS DUTY CONTROL CIRCUIT 1 2 3 VSS VCL Pin Description Pin No. Symbol 1 2 3 4 VSS VCK CLK VDD Description GND 5V power supply Clock input 9V power supply > 100k Impedance [Ω] Pin No. Symbol 5 6 7 8 OUT FEED Description Signal output Impedance [Ω] 600 to 1k CLK Feedback DC output > 100k 10k > 100k AUTO Autobias DC output IN Signal input –2– VDD CXL5001M/P Electrical Characteristics (Ta = 25°C, VDD = 9.0V, VCL = 5.0V, fCLK = 10.7MHz, VCLK = 250mVp-p sine wave, See "Electrical characteristics measuring circuit") Item Symbol IDD ICL Measuring condition 250kHz, 1.28Vp-p, sine wave input 250kHz, 1.28Vp-p, sine wave input IG = 20 log (Output voltage [Vp-p] / 1.28 [Vp-p]) Dissipation at 3.5MHz in relation to 250kHz fG = 20 log (V3.58MHz/ V250kHz) (Note 1) 5-staircase wave input Y = 140 IRE (=1.0Vp-p) Measure S point with vector scope (Note 2) SW conditions Measuring point 1 2 a a A1 A2 Min. — — Typ. Max. Unit 4 9 5 11 mA mA Supply current Insertion gain IG a a V1 –3 0 3 dB Frequency response fG b, c b V1 –3.0 –2.1 — dB Differential gain DG — e a S — — — — — 3 3 — 5 5 % deg Differential phase DP Allowable input amplitude VIN-AC 1.28 Vp-p Noise S/N S: Input = 250kHz, 1.0Vp-p output (Vp-p) N: Input = DC ground output (mVrms) f a V2 55 60 — dB d d a a V2 V3 V4 V5 V6 3.5 3.5 1.3 1.7 5.0 5.0 2.3 2.7 6.5 6.5 3.3 3.7 V V V V VIN-AC Output DC voltage VAUTO-DC VFEED-DC 250kHz, 1.28Vp-p, VOUT-DC sine wave input a a –3– Electrical Characteristics Measuring Circuit V4 SW1 0.01µF 0.1µF LPF Note 3) SW2 8 7 6 5 V1 V6 BPF Note 4) V2 0.1µF 5.1k V5 9V S Vector scope a. 250kHz, 1.28Vp-p sine wave b. 250kHz, 300mVp-p sine wave c. 3.58MHz, 300mVp-p sine wave d. Ground f. CXL5001M/P 250kHz, 1.0Vp-p sine wave 1MΩ 100k VSS VCL –4– 1 2 3 4 A2 A1 9V 0.01µF CLK fCLK = 10.7MHz VCLK = 250mVp-p sine wave 5V CLK VDD VBIAS AUTO FEED OUT e. V3 5-staircase wave IN a b CXL5001M/P CXL5001M/P Note 1) Frequency response measuring condition V3.58MHz (Output signal voltage [Vp-p] at 3.58MHz input) V250kHz (Output signal voltage [Vp-p] at 250kHz input) Set Pin 8 (IN) voltage [V] = VIN-DC + 640mV. [V] 3.58MHz, 300mVp-p sine wave 250kHz, 300mVp-p sine wave 640mV (adjust with VBIAS) VIN-DC Note 2) Differential gain and differential phase measuring condition 5-staircase wave signal Chroma 40 IRE 140 IRE (1.0Vp-p) 40 IRE 1H 63.5µs DG and DP are measured at output S point by vector scope. Note 3) LPF frequency response (Delay time [dB] 0 –3 140ns) Note 4) BPF frequency response [dB] 0 –3 –50 0 5.8 10.7 Frequency [MHz] –50 0 50 200 4.1M 10.7M Frequency [Hz] –5– CXL5001M/P Application Circuit 9V 5.1k 0.01µF 0.1µF Composite video signal input 8 1MΩ 7 6 5 2SA1175 CXL5001M/P 0.1µF L. P. F 1H delay signal output Delay time = 140ns 1 0.01µF 47µF 0.01µF 47µF 2 3 4 0.01µF CLK fCLK = 10.7MHz VCLK = 250mVp-p sine wave 5V 9V Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. Example of Representative Characteristics Frequency response vs. Ambient temperature 0 Input = 300mVp-p 3.58MHz, sine wave 0 Frequency response vs..


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