Document
CXA1875AP/AM
8-bit D/A Converter Compatible with I2C Bus
Description The CXA1875AP/AM is developed as a 8-bit 5 ch D/A converter compatible with I2C bus. Features • Serial control through I2C bus • 4 built-in general purpose I/O ports (Digital I/O) • I/O can be specified to respective ports independently • Selection of 8 slave addresses possible through address select pins (3 pins) Applications I2C bus can control ICs that do not correspond to I2C bus by connecting the DC control pins of them. Structure Bipolar silicon monolithic IC 16 pin DIP (Plastic) 16 pin SOP (Plastic)
Absolute Maximum Ratings (Ta=25°C) • Supply voltage VCC 7 • Operating temperature Topr –20 to +75 • Storage temperature Tstg –65 to +150 • Allowable power dissipation PD 960 Operating Conditions • Supply voltage VCC • Operating temperature Topr
V °C °C mW
5±0.5 –20 to +75
V °C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E94X27-TE
CXA1875AP/AM
Pin Configuration (Top View)
I2C bus VCC 16 SCL 15 SDA 14
Slave address select pin SAD2 13 SAD1 12 SAD0 11
SW I/O SW3 10 SW2 9
1 SW1
2 SW0
3 DAC4
4 DAC3
5 DAC2
6 DAC1
7 DAC0
8 GND
SW I/O
DAC output
Block Diagram
SAD2 SAD1 SAD0 Level Conversion SW0-3 Open collector LATCH Level Conversion
I2C BUS SDA SCL Level Conversion I2C Decoder Power on Reset
LATCH
LATCH
LATCH
LATCH
LATCH
VCC VCC
DAC
DAC
DAC
DAC
DAC
REG
AMP
AMP
AMP
AMP
AMP
GND
DAC4
DAC3
DAC2
DAC1
DAC0
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CXA1875AP/AM
Pin Description No. 1 2 9 10 14 15 Symbol SW1 SW0 SW2 SW3 SDA SCL Equivalent circuit
VCC
150
Description I/O pin for general purpose I/O port VILmax: 1.5 V VIHmin: 3 V VOLmax: 0.4 V SDA I/O pin for I2C bus
4.5k
VCC
3 4 5 6 7
DAC4 DAC3 DAC2 DAC1 DAC0
VCC
56 20k 20k
22k
D/A converter output pin
8
GND
VCC VCC
GND pin Slave address input pin Input at positive logic VILmax: 1.5 V VIHmin: 3 V
4.5k
11 12 13
SAD0 SAD1 SAD2
150
16
VCC
Power supply pin
Electrical Characteristics (Ta=25 °C, VCC=5 V) D/A Converter Block Test No. Item Symbol Test contents circuit 1 Circuit current ICC 1 DAC 0 to 4=127 V(DAC0 to 4=n+1)–V(DAC0 to 4=N) ×128–1 V(DAC0 to 4=191)–V(DAC0 to 4=63) n=0 to 127 DAC 0 to 4=0 DAC 0 to 4=255 Current that can be flowed from Pins 3 to 7 V(–1 mA) –V(1 mA) DAC 0 to 4=127, 2 mA —3—
Min. Typ. Max. Unit 6 9 12 mA
2
Differential linearity Minimum output voltage Maximum output voltage Output current Output impedance
DLE
1
–1
0
+1
LSB
3 4 5 6
Vmin Vmax Iout Z0
1 1 2 2
0.1 4.3 –1 0
0.4 4.6
0.7 4.9 +1
V V mA Ω
3
6
CXA1875AP/AM
SW, SAD Pins No. 7 8 9 10 11 Item Low level input voltage High level input voltage Low level input current High level input current Low level input voltage Symbol VIL VIH IIL IIH VOL Text circuit 3 3 3 3 4 Test contents ST 0 to 3 an input voltage that turns to ‘0’ ST 0 to 3 an input voltage that turns to ‘1’ Input current when 0.4 V is applied Input current when 4.5 V is applied SW 0 to 3=1, Output voltage when 1 mA flows in Min. Typ. Max. Unit — 3.0 –10 –10 0 — — 0 0 0.2 1.5 — +10 +10 0.4 V V µA µA V
I2C Bus Block Items (SDA, SCL) No. 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Item High level input voltage Low level input voltage High level input current Low level input current Low level output voltage At 3 mA flow to SDA (Pin 14) Maximum flowing current Input capacitance Maximum clock frequency Data change minimum waiting time Data transfer start minimum waiting time Low level clock pulse width High level clock pulse width Minimum start preparation waiting time Minimum data hold time Minimum data preparation time Rise time Fall time Minimum stop preparation waiting time VIH VIL IIH IIL VOL IOL CI fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO Symbol Min. Typ. Max. Unit 3.0 0 — — 0 3 — 0 4.7 4.0 4.7 4.0 4.7 5 250 — — 4.7 — — — — — — — — — — — — — — — — — — 5.0 1.5 10 10 0.4 — 10 100 — — — — — — — 1 300 — V V µA µA V mA pF kHz µs µs µs µs µs µs ns µs ns µs
I2C bus load conditions: Pull up resistance 4 kΩ (Connected to +5 V) Load capacitance 200 pF (Connected to GND)
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CXA1875AP/AM
I2C Bus Control Signal
SDA
tBUF SCL
tR
tF
tHD:STA
tHD:STA P S
tLOW
tHD:DAT
tHIGH
tSU:STA tSU:DAT Sr
tSU:STO P
Electrical Characteristics Test Circuit Test circuit 1
I2C BUS +5V A 10µ 0.022µ 5V
Test circuit 2
I2C BUS +5V A 10µ 0.022µ
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
100p
100p 100p 100p
100p
100p
100p 100p 100p
100p
V
V
±1mA
Test circuit 3
I2C BUS +5V 10µ 16 15 14 13 12 11 10 0.022µ A V4
Test circuit 4
I2C BUS +5V 10µ 16 15 14 13 12 11 10 0.022µ 1mA
9
9
V
1
2
3
4
5
6.