Document
CY7C1354BV25 CY7C1356BV25
256K x 36/512K x 18 Pipelined SRAM with NoBL™ Architecture
Features
• Pin-compatible and functionally equivalent to ZBT™ • Supports 225-MHz bus operations with zero wait states — Available speed grades are 225, 200 and 166 MHz • Internally self-timed output buffer control to eliminate the need to use asynchronous OE • Fully registered (inputs and outputs) for pipelined operation • Byte Write capability • Single 2.5V power supply • Fast clock-to-output times — 2.8 ns (for 225-MHz device) — 3.2ns (for 200-MHz device) — 3.5 ns (for 166-MHz device) • Clock Enable (CEN) pin to suspend operation • Synchronous self-timed writes • Available in 100 TQFP, 119 BGA, and 165 fBGA packages • IEEE 1149.1 JTAG Boundary Scan • Burst capability—linear or interleaved burst order • “ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1354BV25 and CY7C1356BV25 are 2.5V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354BV25 and CY7C1356BV25 are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1354BV25 and CY7C1356BV25 are pin compatible and functionally equivalent to ZBT devices. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Write operations are controlled by the Byte Write Selects (BWa–BWd for CY7C1354BV25 and BWa–BWb for CY7C1356BV25) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence.
Logic Block Diagram-CY7C1354BV25 (256K x 36)
A0, A1, A MODE
CLK CEN
ADDRESS REGISTER 0
A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC ADV/LD C
C
WRITE ADDRESS REGISTER 1
WRITE ADDRESS REGISTER 2
ADV/LD
BWa BWb BWc BWd
WE
WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC
WRITE DRIVERS
MEMORY ARRAY
S E N S E A M P S
O U T P U T R E G I S T E R S
D A T A S T E E R I N G
O U T P U T B U F F E R S
E
DQs DQPa DQPb DQPc DQPd
E
INPUT REGISTER 1
E
INPUT REGISTER 0
E
OE CE1 CE2 CE3
ZZ
READ LOGIC
SLEEP CONTROL
Cypress Semiconductor Corporation Document #: 38-05292 Rev. *E
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3901 North First Street
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San Jose, CA 95134 • 408-943-2600 Revised A.