Document
PRELIMINARY
CY7C9235
SMPTE-259M/DVB-ASI Scrambler/Controller
Features
• Fully compatible with SMPTE-259M — SMPTE-125M compliant for 4:2:2 component video — SMPTE-244M compliant for 4 fsc composite video Fully compatible with DVB-ASI Operates from a single +5V or –5V supply 44-pin PLCC package Encodes both 8- and 10-bit parallel digital streams for any rate from 16–40 M characters/sec (160–400 Mbits/sec serial) • Operates with CY7B9234 SMPTE HOTLink™ serializer/transmitter • X9 + X4 + 1 scrambler and NRZI encoder may be bypassed for raw data output • • • • a CY7B9234 HOTLink transmitter, which then converts the bit-parallel characters into a SMPTE-259M compatible high-speed serial data stream. This device performs both TRS (sync) detection and filtering, data scrambling with the SMPTE-259M X 9 + X4 + 1 algorithm, and NRZ-to-NRZI encoding. These functions operate at any character rate from 16- to 40 MHz. For those systems operating with non-SMPTE-259M compliant video streams (or for diagnostic purposes), the scrambler and NRZI encoding functions can be disabled. DVB-ASI Operation The CY7C9235 also contains the necessary multiplexers, control inputs, and outputs, to sequence out a DVB-ASI compliant video stream. DVB-ASI operation is enabled through activation of a single input signal. This allows a single serial output port to support both SMPTE and DVB data streams under software or hardware control. In DVB-ASI mode the CY7C9235 operates with two enable signals (ENA and ENN) to allow data to be presented from either synchronous (clocked) or asynchronous FIFOs. When data is not available, the CY7C9235 ensures that the proper fill character (K28.5) is generated by the attached CY7B9234 serializer. The CY7C9235 operates from a single +5V or −5V supply. It is available in a 44-pin PLCC space saving package.
Functional Description
SMPTE-259M Operation The CY7C9235 is a CMOS integrated circuit designed to encode SMPTE-125M and SMPTE-244M bit-parallel digital characters (or other data formats) using the SMPTE-259M encoding rules. Following encoding, the characters are output as bit-parallel characters ready for serialization. The encoded outputs of the CY7C9235 are designed to be directly mated to
Logic Block Diagram
PD 9 (SVS) TRS_DET
TRS FILTER / DETECTOR
PD 8 PD 7 PD 6 PD 5 PD 4 PD 3 PD 2 PD 1 PD 0 (SC/D) TRS_FILT SC/D_EN SVS_EN BYPASS DVB_EN ENA ENN
Q 9 (SVS)
SMPTE SCRAMBLER
Q8
10
NRZI ENCODER
10
10
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q 0 (SC/D)
10 INPUT REGISTER
10
MODE MULTIPLEXOR
OUTPUT REGISTER
ENA_OUT
CKW OE
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600 March 19, 1999
PRELIMINARY
HOTLink is a trademark of Cypress Semiconductor Corporation.
CY7C9235
Pin Configuration
Q 9 (SVS)
V CC
V SS
Q8
Q7
Q6
Q5
Q4
Q3
Q2 41
6 TRS_DET TRS_FILT SVS_EN OE V SS V SS V SS BYPASS DVB_EN NC PD 9 (SVS) 7 8 9 10 11 12 13 14 15 16 17 18 PD 8
5
4
3
2
1
44
43
42
40 39 Q 0 (SC/D) ENA_OUT ENN ENA CKW V SS V SS V SS SC/D_EN NC NC
NC
Q1 38 37 36 35 34 33 32 31 30 29 28 PD 0 (SC/D)
PLCC Top View
19 PD 7
20 PD 6
21 PD 5
22 V CC
23 V SS
24 PD 4
25 PD 3
26 PD 2
27 PD 1
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... −40°C to +125°C Supply Voltage to Ground Potential..................−0.5V to +7.0V DC Voltage Applied to Outputs in High-Z State .....................................................− 0.5V to +7.0V Output Current into Outputs......................................... 16 mA DC Input Voltage .................................................− 0.5V to +7.0V Static Discharge Voltage .............................................. > 2001 V (per MIL-STD-883, Method 3015) DC Input Current .............................................................± 20 mA Latch-Up Current ............................................................>200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0°C to +70°C −40°C to +85°C VCC 5V ± 5% 5V ± 10%
2
PRELIMINARY
Pin Descriptions
CY7C9235 SMPTE-259M Encoder Name ENA I/O Input Description
CY7C9235
Enable Parallel Data. If ENA is LOW at the rising edge of CKW, the data present on the PD0−9 inputs is latched, and routed to the Q 0–9 outputs. This pin is only interpreted when DVB_EN is active (LOW). If the CY7C9235 is only used in SMPTE-259M mode this signal should be tied to V SS. Enable Next Parallel Data. If ENN is LOW at the rising edge of CKW, the data present on the PD0–9 inputs at the next rising edge of TXCLK is latched, and routed to the Q 0–9 outputs. This pin is only interpreted when DVB_EN is active (LOW). If the CY7C9235 is only used in SMPTE-259M mode this signal should be tied to V SS. Bypass SMPTE Encoding. BYPASS is ignored if DVB_EN is active (LOW). If BYPASS is HIGH at the rising edge of CKW (and DVB_EN is HIGH), the data latched into the input register is routed ar.