Document
PRELIMINARY
Am79C989
Quad Ethernet Switching Transceiver (QuEST™)
DISTINCTIVE CHARACTERISTICS
s Four independent 10BASE-T transceivers compliant with the IEEE 802.3 standard s Four digital Manchester Encode/Decode (MENDEC) units s On-chip filtering enables FCC EMI compliance without external filters or common mode chokes s Automatic polarity Correction and Detection on 10BASE-T receivers s Optional Attachment Unit Interface (AUI) for non-10BASE-T transceivers s 10BASE-T Extended Distance option accommodate lines longer than 100 meters s Quad AMD Switching Interface (QuASI™) interface reduces overall pin count s Half-Duplex and Full-Duplex operation s Auto-Negotiation compliant with IEEE 802.3u Standard s Standard MII management interface and protocol s Status Change Interrupt output pin for fast response time to changed conditions s 44-pin PLCC CMOS device s 5 V supply with 3.3 V system interface compatibility
GENERAL DESCRIPTION
The Am79C989 Quad Ethernet Switching Transceiver (QuEST™) is a four-port physical layer (PHY) device that provides all of the analog functions needed for a 10BASE-T switch, including four independent Manchester Encode/Decode units (MENDECs) and four independent 10BASE-T transceivers. If the AUI p o rt i s u s e d fo r a 1 0 B A S E - 2 , 1 0 B A S E - 5 , o r 10BASE-FL transceiver, one of the four 10BASE-T ports is disabled. The QuEST device is designed for 10 Mbps Ethernet switching hubs, port switching repeater hubs, routers, bridges, and servers that require data encoding and clock recovery on a per port basis and are limited by pin constraints. Clock recovery is performed as part of the MENDEC function. The QuEST device supports every physical layer function of a full-featured switch, including full-duplex operation with Auto-Negotiation and the ability to use various media types. A unique feature of the QuEST device is the Quad AMD Switching Interface (QuASI) which multiplexes the data for all four channels into one set of pins. This minimizes the pin count and size of the QuEST device and substantially reduces overall system cost. The QuEST device provides a 2-pin Media Independent Interface (MII) Management Interface which supports the protocols specified in the IEEE 802.3u standard. Controlled by the switch system, this interface allows the QuEST device to be polled for status information and allows operating parameters of the QuEST device, such as extended distance operation, to be altered. The Am79C989 device provides an Interrupt pin to indicate changes in the internal status of the device. The interrupt function reduces CPU polling of status registers and allows fast response time to changes in physical layer conditions.
This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
Publication# 21173 Rev: B Amendment/+2 Issue Date: April 1997
P R E L I M I N A R Y
BLOCK DIAGRAM
System Interface
Network Interface
10BASE-T Transceiver 0 Jabber Timer QTX_EN Collision Detect Manchester Encoder Line Driver with Wave Shaping
TXD0+ TXD0-
RXD0+ QTX_DATA Manchester Decode and Carrier Detect Elasticity FIFO QRX_DATA QRX_VALID QuASI Interface 10BASE-T Transceiver 1 Link Detect Link/Auto Neg State Machine Polarity Detection/ Correction Line Receiver with Smart Squelch RXD0-
REXT
QRX_CRS
TXD1+ TXD1RXD1+ RXD1TXD2+ TXD2RXD2+ RXD2TXD3+ TXD3RXD3+ RXD3PCI/CI+
QCLSN
10BASE-T Transceiver 2
10BASE-T Transceiver 3
SCLK
Collision Detect
AUI Collision Squelch
QINT/CI-
DO+ QRST/STRB Attachment Unit Interface AUI Receiver with Squelch AUI Transmitter DODI+ DI-
Register Block
MDC MDIO v3 Management Interface
21173B-1
2
Am79C989
P R E L I M I N A R Y
CONNECTION DIAGRAM
QRX_VALID
QRX_DATA
QTX_DATA
QRX_CRS
QTX_EN
QCLSN
VDDIO
VSSIO
SCLK
MDIO
6 QRST/STRB REXT VSS QINT/CIPCI/CI+ DIDI+ VSSAUI DODO+ VDDTX 7 8 9 10 11 12 13 14 15 16 17
5 4
3 2
1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDD RXD3+ RXD3RXD2+ RXD2VSSRX RXD1+ RXD1RXD0+ RXD0VDDTX
QuEST Am79C989 44 PLCC Version 2.0
18 19 20 21 22 23 24 25 26 27 28 VSSTX VDDTX VSSTX TXD0TXD1TXD+ TXD2TXD0+ TXD2+ TXD3TXD3+
MDC
21173B-2
Am79C989
3
P R E L I M I N A R Y
LOGIC DIAGRAM
QTX_EN QTX_DATA QRX_DATA QRX_VALID QRX_CRS QCLSN SCLK QRST/STRB MDC MDIO VSS
VDDIO
VDDTX(3)
VDD
TXD+ TXDTwisted Pair Ports (4 Ports) RXD+ RXDQINT/CIPCI/CI+ DO+ DODI+
VSSAUI
VSSTX(2)
VSSRX
VSSIO
DI-
21173B-3
LOGIC SYMBOL
MENDEC
TP
MENDEC QuASI QuASI Interface
TP
MENDEC
TP
TP MENDEC
AUI
Management Interface
21173B-4
4
Am79C989
P R E L I M I N A R Y
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