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AM29SL800C Dataheets PDF



Part Number AM29SL800C
Manufacturers Advanced Micro Devices
Logo Advanced Micro Devices
Description 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory
Datasheet AM29SL800C DatasheetAM29SL800C Datasheet (PDF)

PRELIMINARY Am29SL800C 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory DISTINCTIVE CHARACTERISTICS s Single power supply operation — 1.8 to 2.2 V for read, program, and erase operations — Ideal for battery-powered applications s Manufactured on 0.32 µm process technology — Compatible with 0.35 µm Am29SL800B device s High performance — Access times as fast as 100 ns s Ultra low power consumption (typical values at 5 MHz) — 65 nA Automatic Sleep Mode curre.

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PRELIMINARY Am29SL800C 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory DISTINCTIVE CHARACTERISTICS s Single power supply operation — 1.8 to 2.2 V for read, program, and erase operations — Ideal for battery-powered applications s Manufactured on 0.32 µm process technology — Compatible with 0.35 µm Am29SL800B device s High performance — Access times as fast as 100 ns s Ultra low power consumption (typical values at 5 MHz) — 65 nA Automatic Sleep Mode current — 65 nA standby mode current — 5 mA read current — 10 mA program/erase current s Flexible sector architecture — One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and fifteen 64 Kbyte sectors (byte mode) — One 8 Kword, two 4 Kword, one 16 Kword, and fifteen 32 Kword sectors (word mode) — Supports full chip erase — Sector Protection features: A hardware method of locking a sector to prevent any program or erase operations within that sector Sectors can be locked in-system or via programming equipment Temporary Sector Unprotect feature allows code changes in previously locked sectors s Unlock Bypass Program Command — Reduces overall programming time when issuing multiple program command sequences s Top or bottom boot block configurations available s Embedded Algorithms — Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors — Embedded Program algorithm automatically writes and verifies data at specified addresses s Minimum 1,000,000 write cycle guarantee per sector s Package option — 48-pin TSOP — 48-ball FBGA s Compatibility with JEDEC standards — Pinout and software compatible with singlepower supply Flash — Superior inadvertent write protection s Data# Polling and toggle bits — Provides a software method of detecting program or erase operation completion s Ready/Busy# pin (RY/BY#) — Provides a hardware method of detecting program or erase cycle completion s Erase Suspend/Erase Resume — Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation s Hardware reset pin (RESET#) — Hardware method to reset the device to reading array data This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 22230 Rev: A Amendment/0 Issue Date: August 1998 Refer to AMD’s Website (www.amd.com) for the latest information. P R E L I M I N A R Y GENERAL DESCRIPTION The Am29SL800C is an 8 Mbit, 1.8 V volt-only Flash memory organized as 1,048,576 bytes or 524,288 words. The device is offered in 48-pin TSOP and 48ball FBGA packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed and erased in-system with a single 1.8 volt V CC supply. No VPP is for write or erase operations. The device can also be programmed in standard EPROM programmers. The standard device offers access times of 100, 120, and 150 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 1.8 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The se.


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