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CY28343

Cypress Semiconductor

Zero Delay SDR/DDR Clock Buffer


Description
CY28343 Zero Delay SDR/DDR Clock Buffer Features Phase-lock loop clock distribution for DDR and SDR SDRAM applications One-single-end clock input to 6 pairs DDR outputs or 13 SDR outputs. External feedback pins FBIN_SDR/FBOUT_SDR are used to synchronize the outputs to the clock input for SDR. Table 1. Function Table SELDDR_SDR# 1= DDR Mode CLKIN 2.5V ...



Cypress Semiconductor

CY28343

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