Document
CXP81720B/81724B
CMOS 8-bit Single Chip Microcomputer
Description The CXP81720B/81724B is a CMOS 8-bit microcomputer which consists of A/D converter, serial interface, timer/counter, time-base timer, highprecision timing pattern generation circuit, PWM output, 32kHz timer/counter, remote control reception circuit, as well as basic configurations like 8-bit CPU, ROM, RAM and I/O port. They are integrated into a single chip. Also CXP81720B/81724B provides sleep/stop functions which enables to lower power consumption. 100 pin QFP (PIastic) 100 pin LQFP (PIastic)
Structure Silicon gate CMOS IC
Features • A wide instruction set (213 instructions) which covers various types of data — 16-bit arithmetic/multiplication and division/Boolean bit operation instructions • Minimum instruction cycle 250ns at 16MHz operation (4.5 to 5.5V) 122µs at 32kHz operation (2.7 to 5.5V) • Incorporated ROM capacity 20K bytes (CXP81720B) 24K bytes (CXP81724B) • Incorporated RAM capacity 800 bytes • Peripheral functions — A/D converter 8 bits, 12 channels, successive approximation method (Conversion time of 20.0µs at 16MHz) — Serial interface Incorporated 8-bit and 8-stage FIFO, 1 channel (Auto transfer for 1 to 8 bytes) 8-bit clock sync type, 1 channel — Timer 8-bit timer, 8-bit timer/counter, 19-bit time-base timer 32kHz timer/counter — High-precision timing pattern generator PPG: maximum of 19 pins, 32 stages programmable RTG: 5 pins, 2 channels — PWM/DA gate output PWM: 12 bits, 2 channels (Repetitive frequency 62kHz/16MHz) DA gate pulse output: 12 bits, 4 channels — FRC capture unit Incorporated 26-bit and 8-stage FIFO — PWM output 14 bits, 1 channel — Remote control reception circuit 8-bit pulse measuring counter, 6-stage FIFO • Interruption 20 factors, 15 vectors, multi-interruption possible • Standby mode Sleep/stop • Package 100-pin plastic QFP/LQFP • Piggyback/evaluator CXP81800
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E97737-PS
Block Diagram
TEX TX EXTAL XTAL RST MP VDD Vss AVREF AVss INT1/NMI INT2 INT0
2 8 SPC700 CPU CORE
PORT B
AVDD
CLOCK GENERATOR/ SYSTEM CONTROL 8
PORT A
AN0 to AN11
12
A/D CONVERTER
NMI
PA0 to PA7
PB0 to PB7
CS0 SI0 SO0 SCK0 FIFO ROM 20K/24K BYTES RAM 800 BYTES
PORT C
SERIAL INTERFACE UNIT (CH0)
INTERRUPT CONTROLLER
8
PC0 to PC7
PORT D
SI1 SO1 SCK1 2
SERIAL INTERFACE UNIT (CH1)
8
PD0 to PD7
2 6 4 4
PE0 to PE1 PE2 to PE7 PF0 to PF3
TO
8 BIT TIMER 1
PORT F
32kHz TIMER/COUNTER
PORT G
2
PORT H
12 BIT PWM GENERATOR CH0 2
PWM0 DAA0 DAB0 PWM1 DAA1 DAB1 4 19
CH0 5
CH1
ADJ
PPO0/PPO18
RTO3/RTO7
PORT J
12 BIT PWM GENERATOR CH1
PROGRAMMABLE PATTERN GENERATOR
RAM
REAL.