Document
HM62W16255HC Series
4M High Speed SRAM (256-kword × 16-bit)
ADE-203-1200 (Z) Preliminary Rev. 0.0 Sep. 1, 2000 Description
The HM62W16255HC is a 4-Mbit high speed static RAM organized 256-kword × 16-bit. It has realized high speed access time by employing CMOS process (6-transistor memory cell) and high speed circuit designing technology. It is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. The HM62W16255HC is packaged in 400-mil 44-pin SOJ and 400-mil 44-pin plastic TSOPII for high density surface mounting.
Features
• Single 3.3 V supply: 3.3 V ± 0.3 V • Access time: 10 ns (max) • Completely static memory No clock or timing strobe required • Equal access and cycle times • Directly TTL compatible All inputs and outputs • Operating current: 145 mA (max) • TTL standby current: 40 mA (max) • CMOS standby current: 5 mA (max) : 1 mA (max) (L-version) • Data retention current: 0.6 mA (max) (L-version) • Data retention voltage: 2.0 V (min) (L-version) • Center VCC and VSS type pinout
Preliminary: The specification of this device are subject to change without notice. Please contact your nearest Hitachi’s Sales Dept. regarding specification.
HM62W16255HC Series
Ordering Information
Type No. HM62W16255HCJP-10 HM62W16255HCLJP-10 HM62W16255HCTT-10 HM62W16255HCLTT-10 Access time 10 ns 10 ns 10 ns 10 ns 400-mil 44-pin plastic TSOPII (TTP-44DE) Package 400-mil 44-pin plastic SOJ (CP-44D)
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HM62W16255HC Series
Pin Arrangement
44-pin SOJ
A0 A1 A2 A3 A4 CS I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE UB LB I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A14 A13 A12 A11 A10 A0 A1 A2 A3 A4 CS I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44-pin TSOP
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE UB LB I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A14 A13 A12 A11 A10
(Top View)
(Top View)
Pin Description
Pin name A0 to A17 I/O1 to I/O16 CS OE WE UB LB VCC VSS NC Function Address input Data input/output Chip select Output enable Write enable Upper byte select Lower byte select Power supply Ground No connection
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HM62W16255HC Series
Block Diagram
(LSB) A14 A13 A12 A5 A6 A7 A11 A10 A3 (MSB) A1 I/O1 . . . I/O8 I/O9 . . . I/O16 WE CS LB UB
VCC Row decoder Memory matrix 1024 rows × 32 columns × 8 blocks × 16 bit (4,194,304 bits) VSS
CS Column I/O Input data control Column decoder CS
(LSB) A8 A9 A17 A15 A16 A0 A2 A4 (MSB)
OE
CS
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HM62W16255HC Series
Operation Table
CS H L L L L L L L L L Note: OE × H L L L L × × × × WE × H H H H H L L L L ×: H or L LB × × L L H H L L H H UB × × L H L H L H L H Mode Standby Output disable Read VCC current I SB , I SB1 I .