HM628512C

HM628512C Series 4 M SRAM (512-kword × 8-bit) ADE-203-1212 (Z) Preliminary Rev. 0.0 Sep. 12, 2000 Description The Hitachi HM628512C is a 4-Mbit static RAM organized 512-kword × 8-bit. It realizes higher density, higher performance and low power consumption by employing Hi-CMOS process technology. The device, packaged in a 525-mil SOP (foot print pitch width) or 400-mil TSOP TYPE II or 600-mil plastic DIP, is available for high density mounting. The HM628512C is suitable for battery backup system. Features Single 5 V supply Access time: 55/70 ns (max) Power dissipation  Active: 50 mW/MHz (typ)  Standby: 10 µW (typ) Completely static memory. No clock or timing strobe required Equal access and cycle times Common data input and output: Three state output Directly TTL compatible: All inputs and outputs Battery backup operation Preliminary: The specification of this device are subject to change without notice. Please contact your nearest Hitachi’s Sales Dept. regarding specification. HM628512C Series Ordering Information Type No. HM628512CLP-5 HM628512CLP-7 HM628512CLP-5SL HM628512CLP-7SL HM628512CLFP-5 HM628512CLFP-7 HM628512CLFP-5SL HM628512CLFP-7SL HM628512CLTT-5 HM628512CLTT-7 HM628512CLTT-5SL HM628512CLTT-7SL HM628512CLRR-5 HM628512CLRR-7 HM628512CLRR-5SL HM628512CLRR-7SL Access time 55 ns 70 ns 55 ns 70 ns 55 ns 70 ns 55 ns 70 ns 55 ns 70 ns 55 ns 70 ns 55 ns 70 ns 55 ns 70 ns 400-mil 32-pin plastic TSOP II reverse (TTP-32DR) 400-mil 32-pin plastic TSOP ...