HM1-6508B883

HM-6508/883 March 1997 1024 x 1 CMOS RAM Description The HM-6508/883 is a 1024 x 1 static CMOS RAM fabricated using self-aligned silicon gate technology. Synchronous circuit design techniques are employed to achieve high performance and low power operation. On chip latches are provided for address allowing efficient interfacing with microprocessor systems. The data output buffers can be forced to a high impedance state for use in expanded memory arrays. The HM-6508/883 is a fully static RAM and may be maintained in any state for an indefinite period of time. Data retention supply voltage and supply current are guaranteed over temperature. Features This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. Low Power Standby . . . . . . . . . . . . . . . . . . . . 50µW Max Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 180ns Max Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . .2.0V Min TTL Compatible Input/Output High Output Drive - 2 TTL Loads On-Chip Address Register Ordering Information PACKAGE CERDIP TEMP. RANGE 180ns 250ns PKG. NO. F16.3 -55oC to +125oC HM1HM16508B/883 6508/883 Pinout HM1-6508/883 (CERDIP) TOP VIEW E 1 A0 2 A1 3 A2 4 A3 5 A4 6 Q 7 GND 8 16 VCC 15 D 14 W 13 A9 12 A8 11 A7 10 A6 9 A5 PIN A E W D Q DESCRIPTION Address Input Chip Enable Write Enable Data Input Data Output CAUTION: These dev...