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HM-65162 Dataheets PDF



Part Number HM-65162
Manufacturers Intersil Corporation
Logo Intersil Corporation
Description 2K x 8 Asynchronous CMOS Static RAM
Datasheet HM-65162 DatasheetHM-65162 Datasheet (PDF)

HM-65162 March 1997 2K x 8 Asynchronous CMOS Static RAM Description The HM-65162 is a CMOS 2048 x 8 Static Random Access Memory manufactured using the Intersil Advanced SAJI V process. The device utilizes asynchronous circuit design for fast cycle time and ease of use. The pinout is the JEDEC 24 pin DIP, and 32 pad 8-bit wide standard which allows easy memory board layouts flexible to accommodate a variety of industry standard PROMs, RAMs, ROMs and EPROMs. The HM-65162 is ideally suited for use .

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HM-65162 March 1997 2K x 8 Asynchronous CMOS Static RAM Description The HM-65162 is a CMOS 2048 x 8 Static Random Access Memory manufactured using the Intersil Advanced SAJI V process. The device utilizes asynchronous circuit design for fast cycle time and ease of use. The pinout is the JEDEC 24 pin DIP, and 32 pad 8-bit wide standard which allows easy memory board layouts flexible to accommodate a variety of industry standard PROMs, RAMs, ROMs and EPROMs. The HM-65162 is ideally suited for use in microprocessor based systems with its 8-bit word length organization. The convenient output enable also simplifies the bus interface by allowing the data outputs to be controlled independent of the chip enable. Gated inputs lower operating current and also eliminate the need for pull-up or pull-down resistors. Features • Fast Access Time. . . . . . . . . . . . . . . . . . . . 70/90ns Max • Low Standby Current. . . . . . . . . . . . . . . . . . . .50µA Max • Low Operating Current . . . . . . . . . . . . . . . . . 70mA Max • Data Retention at 2.0V . . . . . . . . . . . . . . . . . . .20µA Max • TTL Compatible Inputs and Outputs • JEDEC Approved Pinout (2716, 6116 Type) • No Clocks or Strobes Required • Equal Cycle and Access Time • Single 5V Supply • Gated Inputs • No Pull-Up or Pull-Down Resistors Required Ordering Information PACKAGE CERDIP JAN# SMD# CLCC SMD# NOTE: 1. Access time/data retention supply current. TEMP. RANGE -40oC to +85oC -55oC to +125oC -55oC to +125oC -40oC to +85oC -55oC to 125oC 70ns/20µA (NOTE 1) HM1-65162B-9 29110BJA 8403606JA HM4-65162B-9 8403606ZA 90ns/40µA (NOTE 1) HM1-65162-9 29104BJA 8403602JA HM4-65162-9 8403602ZA 8403603JA HM4-65162C-9 8403603ZA 90ns/300µA (NOTE 1) HM1-65162C-9 PKG. NO. F24.6 F24.6 F24.6 J32.A J32.A Pinouts HM-65162 (CERDIP) TOP VIEW NC A7 HM-65162 (CLCC) TOP VIEW VCC PIN NC NC 31 30 29 A8 28 A9 27 NC 26 W 25 G 24 A10 23 E 22 DQ7 21 DQ6 DESCRIPTION No Connect Address Input Chip Enable/Power Down Ground Data In/Data Out Power (+5V) Write Enable Output Enable NC NC A7 A6 A5 A4 A3 A2 A1 A0 DQ0 1 2 3 4 5 6 7 8 9 24 VCC 23 A8 22 A9 21 W 20 G 19 A10 18 E 17 DQ7 16 DQ6 15 DQ5 14 DQ4 13 DQ3 A6 A5 A4 A3 A2 5 6 7 8 9 4 3 2 1 32 NC A0 - A10 E VSS/GND DQ0 - DQ7 VCC W G A1 10 A0 11 NC 12 DQ0 13 14 DQ1 15 16 DQ2 GND 17 NC 18 DQ3 19 DQ4 20 DQ5 DQ1 10 DQ2 11 GND 12 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 File Number 3000.1 6-1 HM-65162 Functional Diagram A1 A A2 A3 A4 A5 A6 A7 ROW ADDRESS BUFFER 7 ROW DECODER A 7 128 COLUMN DECODER AND DATA INPUT / OUTPUT (X8) 4 A G 4 A 1 OF 8 DQ0 THRU DQ7 128 128 X 128 MEMORY ARRAY 8 E COLUMN ADDRESS BUFFER W A0 A8 A9 A10 6-2 HM-65162 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC.


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